Hitachi 16-Bit Single-Chip Microcomputer
H8S/2194 Series, H8S/2194C Series,
™
™
H8S/2194 F-ZTAT , H8S/2194C F-ZTAT
H8S/2194, HD6432194, HD64F2194,
H8S/2193, HD6432193
H8S/2192, HD6432192
H8S/2191, HD6432191
H8S/2194C, HD6432194C, HD64F2194C,
H8S/2194B, HD6432194B
H8S/2194A, HD6432194A
Hardware Manual
ADE-602-160A
Rev. 2.0
11/10/00
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Main Revisions and Additions in this Edition
Page
All pages of
this manual
5
14
1.1 Overview
1.4 Differences between
H8S/2194C Series and
H8S/2194 Series
Item
Revisions (See Manual for Details)
Amendments due to introduction of the H8S/2194C
series
Table 1.1 Features
Memory and Product lineup amended
Added
All pages of
section 2
31
65, 66
68
2.6.1 Overview
3.4 Address Map in Each
Operating Mode
4.1 Overview
Notes on TAS instruction added
Table 2.1 Instruction Classification
Notes 3 added
Address maps for the H8S/2194C series added
Table 4.1 Internal Chip Status in Each Mode
Timer L, PSU, 12-bit PWM added
Sleep and Watch modes of I/O amended
Description amended
Other supporting modules (excluding the servo
circuit and 12-bit PWM) do not stop.
Table 4.4 MSTP Bits and Corresponding On-Chip
Supporting Modules
Module corresponding to the MSTP1 bit amended
Table 6.8 Interrupt Response Times
Note 2 amended
Added
Figure 7.3 Flash Memory Mode Transitions
Amended
Figure 7.4 Boot Mode
Amended
7.3.1 Flash Memory Control
Register 1 (FLMCR1)
Description amended
FLMCR1 is initialized by a reset, in power-down
state (excluding the medium-speed mode, module
stop mode, and sleep mode), or when a low level is
input to the FWE pin.
79
4.4.1 Sleep Mode
80
4.5.1 Module Stop Mode
119
121
126
127
131
6.4.5 Interrupt Response
Times
6.5.4 When NMI is Disabled
7.2.3 Flash Memory
Operating Modes
Rev. 2.0, 11/00, page I of V
Page
134
Item
7.3.2 Flash Memory Control
Register 2 (FLMCR2)
Revisions (See Manual for Details)
Description amended
The ESU and PSU bits are cleared to 0 in power-
down state (excluding the medium-speed mode,
module stop mode, and sleep mode), hardware
protect mode, and software protect mode.
136
7.3.3 Erase Block Registers 1 Description amended
and 2 (EBR1, EBR2)
EBR1 and EBR2 are each initialized to H’00 by a
reset, in power-down state (excluding the medium-
speed mode, module stop mode, and sleep mode),
when a low level is input to the FWE pin, or when a
high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set.
Table 7.4 Flash Memory Erase Blocks
EB3 address amended
138
140
141
7.4 On-Board Programming
Modes
7.4.1 Boot Mode
Table 7.5 Setting On-Board Programming Modes
MD0 pin level in use program mode amended
Figure 7.8 Boot Mode Execution Procedure
Flow amended
Table 7.6 System Clock Frequencies for which
Automatic Adjustment of This LSI Bit Rate is
Possible
2400-bps transfer bit rate deleted
Figure 7.10 RAM Areas in Boot Mode
Programming control program area amended
142
145
146
148
7.5.1 Program Mode
7.5.2 Program-Verify Mode
7.5.3 Erase Mode
7.5.4 Erase-Verify Mode
150
152
7.6.1 Hardware Protection
7.6.3 Error Protection
Description amended
(For details, see the flowchart in figure 7.12.)
Description amended
(For details, see the flowchart in figure 7.12.)
Description amended
(For details, see the flowchart in figure 7.13.)
Description amended
(For details, see the flowchart in figure 7.13.)
Table 7.7 Hardware Protection
Reset/standby protection description amended
FLER bit setting condition (3) amended
Figure 7.14 Flash Memory State Transitions
amended
Note 1 amended
153
7.7 Interrupt Handling when
Programming/Erasing Flash
Memory
7.8.2 Socket Adapters and
Memory Map
154
Table 7.9 Socket Adapter Product Codes
amended
Rev. 2.0, 11/00, page II of V
Page
166
Item
7.8.9 Programmer Mode
Transition Time
Revisions (See Manual for Details)
Figure 7.23 Oscillation Stabilization Time, Boot
Program Transfer Time, and Power Supply Fall
Sequence
Vcc timing amended
169
7.10 Note on Switching from Added
F-ZTAT Version to Mask ROM
Version
Section 8 ROM (H8S/2194C
Series)
9.1 Overview
14.1.2 Block Diagram
Added
Description amended due to introduction of the
H8S/2194C series
Figure 14.1 Block Diagram of the Timer J
φ/1024
clock source (for H8S/2194C series) added
221
304
308
311, 312
336
416
419
420
443
454
520
522
531,
534 to 536
541
544
14.2.1 Timer Mode Register J Bits 3 and 2
(TMJ)
Description amended
14.2.2 Timer J Control
Register (TMJC)
16.2.1 Timer R Mode
Register 1 (TMRM1)
Bit 0 description amended
Bit 0 description amended
20.2.1 12-Bit PWM Control
Initialization description amended
Registers (CPWCR, DPWCR)
20.2.2 12-Bit PWM Data
Initialization description amended
Registers (CPWDR, DPWDR)
20.2.3 Module stop Control
Register (MSTPCR)
23.1.2 Block Diagram
Added
Figure 23.1 Block Diagram of SCI1
Register names amended
23.2.7 Serial Status Register Bit 7:
(SSR1)
Clearing conditions amended
25.1.4 Register Configuration Table 25.2 Register Configuration
Note 2 description amended
25.2.1 I C Bus Data Register
(ICDR)
25.2.5 I C Bus Control
Register (ICCR)
25.2.6 I C Bus Status
Register (ICSR)
25.2.7 Serial/Timer Control
Register (STCR)
2
2
2
Description amended
Bit 7 description amended
Bit 1 description amended
Bit 4 description amended
Bit 5 description amended
Rev. 2.0, 11/00, page III of V
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
