CXD3615R
Timing Generator for Frame Readout CCD Image Sensor
Description
The CXD3615R is a timing generator IC which
generates the timing pulses for performing frame
readout using the ICX432/434 CCD image sensor.
Features
•
Base oscillation frequency 48.6/36.0MHz
•
Electronic shutter function
•
Supports draft, AF mode
•
H/V driver for CCD
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
•
ICX432 (Type 1/2.7, 3240K pixels)
•
ICX434 (Type 1/3.2, 2020K pixels)
Absolute Maximum Ratings
•
Supply voltage
V
DD
VL
VH
•
Input voltage
•
Output voltage
V
SS
– 0.3 to +7.0
–10.0 to V
SS
VL – 0.3 to +26.0
V
V
V
48 pin LQFP (Plastic)
V
I
V
SS
– 0.3 to V
DD
+ 0.3 V
V
SS
– 0.3 to V
DD
+ 0.3 V
V
O1
V
O2
VL – 0.3 to V
SS
+ 0.3 V
V
O3
VL – 0.3 to VH + 0.3 V
•
Operating temperature
Topr
–20 to +75
°C
•
Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
•
Supply voltage V
DD
a, V
DD
b, V
DD
c
3.0 to 3.6
VM
0.0
VH
14.5 to 15.5
VL
–7.0 to –8.0
•
Operating temperature
Topr
–20 to +75
Pin Configuration
MCKO
OSCO
OSCI
V
DD
5
V
SS
5
CKO
SEN
SCK
CKI
SSI
HR
VR
36
VM
V4
V2
V5A
VH
V5B
V1
V3A
VL
V3B
V6
SUB
37
38
39
40
41
42
43
44
45
46
47
48
1
V
SS
1
35
34
33
32
31
30
29
28
27
26
25
24 V
SS
4
23 ADCLK
22 OBCLP
21 TEST2
20 CLPDM
19 PBLK
18 TEST1
17 XSHD
16 XSHP
15 V
DD
4
14 V
DD
3
13 H2
V
V
V
V
°C
∗
Groups of pins enclosed in the figure indicate
sections for which power supply separation is
possible.
2
RST
3
SNCSL
4
ID/EXP
5
WEN/FLD
6
SSGSL
7
V
DD
1
8
V
DD
2
9
RG
10
V
SS
2
11
V
SS
3
12
H1
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02216-PS
CXD3615R
Block Diagram
ADCLK
V
SS
3
H1
H2
11 12 13 14
OSCI
OSCO
28
27
Sel
8
9
10
16 17 23
CKG
19 PBLK
CKI
26
Sel
XSHD
XSHP
V
DD
3
V
DD
2
V
SS
2
RG
20 CLPDM
SHT
H/VTM
22 OBCLP
4
5
ID/EXP
WEN/FLD
1/2
MCKO 30
CKO 25
1/2
SNCSL
3
Selector
Latch
39 V2
38 V4
47 V6
43 V1
44 V3A
SSI 31
SCK 32
SEN 33
Selector
Register
V Driver
46 V3B
40 V5A
42 V5B
48 SUB
37 VM
41 VH
45 VL
SSGSL
6
SSG
RST
2
TEST1 18
TEST2 21
1
V
SS
1
24 36
V
SS
4
V
SS
5
7
V
DD
1
15 29
V
DD
4
V
DD
5
35 34
HR
VR
–2–
CXD3615R
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol
V
SS
1
RST
SNCSL
ID/EXP
WEN/FLD
SSGSL
V
DD
1
V
DD
2
RG
V
SS
2
V
SS
3
H1
H2
V
DD
3
V
DD
4
XSHP
XSHD
TEST1
PBLK
CLPDM
TEST2
OBCLP
ADCLK
V
SS
4
CKO
CKI
OSCO
OSCI
V
DD
5
MCKO
I/O
—
I
I
O
O
I
—
—
O
—
—
O
O
—
—
O
O
I
O
O
—
O
O
—
O
I
O
I
—
O
GND
Internal system reset input.
High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input
Control input used to switch sync system.
High: CKI sync, Low: MCKO sync
With pull-down resistor
Description
Vertical direction line identification pulse output/exposure time identification pulse
output.
Switching possible using the serial interface data. (Default: ID)
Memory write timing pulse output/field discrimination pulse output.
Switching possible using the serial interface data. (Default: WEN)
Internal SSG enable.
High: Internal SSG valid, Low: External sync valid
With pull-down resistor
3.3V power supply. (Power supply for common logic block)
3.3V power supply. (Power supply for RG)
CCD reset gate pulse output.
GND
GND
CCD horizontal register clock output.
CCD horizontal register clock output.
3.3V power supply. (Power supply for H1/H2)
3.3V power supply. (Power supply for CDS)
CCD precharge level sample-and-hold pulse output.
CCD data level sample-and-hold pulse output.
IC test pin 1; normally fixed to GND.
CCD dummy signal clamp pulse output.
IC test pin 2; normally fixed to GND.
With pull-down resistor
CCD optical black signal clamp pulse output.
The horizontal/vertical OB pattern can be changed using the serial interface data.
Clock output for analog/digital conversion IC.
Logical phase adjustment possible using the serial interface data.
GND
Inverter output.
Inverter input.
Inverter output for oscillation. When not used, leave open or connect a capacitor.
Inverter input for oscillation. When not used, fix to low.
3.3V power supply. (Power supply for common logic block)
System clock output for signal processing IC.
With pull-down resistor
Pulse output for horizontal and vertical blanking period pulse cleaning
–3–
CXD3615R
Pin
No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Symbol
SSI
SCK
SEN
VR
HR
V
SS
5
VM
V4
V2
V5A
VH
V5B
V1
V3A
VL
V3B
V6
SUB
I/O
I
I
I
I/O
I/O
—
—
O
O
O
—
O
O
O
—
O
O
O
Description
Serial interface data input for internal mode settings.
Schmitt trigger input
Serial interface clock input for internal mode settings.
Schmitt trigger input
Serial interface strobe input for internal mode settings.
Schmitt trigger input
Vertical sync signal input/output.
Horizontal sync signal input/output.
GND
GND (GND for vertical driver)
CCD vertical register clock output/V2 for ICX434.
CCD vertical register clock output/open for ICX434.
CCD vertical register clock output/V3A for ICX434.
15.0V power supply. (Power supply for vertical driver)
CCD vertical register clock output/V3B for ICX434.
CCD vertical register clock output/open for ICX434.
CCD vertical register clock output//V1A for ICX434.
–7.5V power supply. (Power supply for vertical driver)
CCD vertical register clock output/V1B for ICX434.
CCD vertical register clock output//V4 for ICX434.
CCD electronic shutter pulse output.
–4–
CXD3615R
Electrical Characteristics
DC Characteristics
Item
Pins
Symbol
V
DD
a
V
DD
b
V
DD
c
Vt
+
Vt
–
0.7V
DD
c
0.3V
DD
c
0.8V
DD
c
0.2V
DD
c
Feed current where I
OH
= –1.2mA V
DD
c – 0.8
Pull-in current where I
OL
= 2.4mA
Feed current where I
OH
= –14.0mA V
DD
a – 0.8
Pull-in current where I
OL
= 9.6mA
Feed current where I
OH
= –3.3mA V
DD
b – 0.8
Pull-in current where I
OL
= 2.4mA
Feed current where I
OH
= –3.3mA V
DD
c – 0.8
Pull-in current where I
OL
= 2.4mA
Feed current where I
OH
= –6.9mA V
DD
c – 0.8
Pull-in current where I
OL
= 4.8mA
Feed current where I
OH
= –3.3mA V
DD
c – 0.8
Pull-in current where I
OL
= 2.4mA
Feed current where I
OH
= –2.4mA V
DD
c – 0.8
Pull-in current where I
OL
= 4.8mA
V1, V2, V3A/B, V4, V5A/B, V6
= –8.25V
V1, V2, V3A/B, V4, V5A/B, V6
= –0.25V
V1, V3A/B, V5A/B = 0.25V
V1, V3A/B, V5A/B = 14.75V
SUB = –8.25V
SUB = 14.75V
5.4
–4.0
5.0
–7.2
10.0
–5.0
0.4
0.4
0.4
0.4
0.4
0.4
0.4
(Within the recommended operating conditions)
Conditions
Min.
3.0
3.0
3.0
0.8V
DD
c
0.2V
DD
c
Typ.
3.3
3.3
3.3
Max.
3.6
3.6
3.6
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
Supply voltage 1 V
DD
3
Supply voltage 2 V
DD
2
Supply voltage 3
V
DD
1, V
DD
4,
V
DD
5
RST, SSI,
Input voltage 1
∗
1
SCK, SEN
TEST1, TEST2, V
IH1
Input voltage 2
∗
2
SNCSL, SSGSL V
IL1
V
IH2
Input/output
voltage
VR, HR
V
IL2
V
OH1
V
OL1
Output voltage 1 H1, H2
Output voltage 2 RG
V
OH2
V
OL2
V
OH3
V
OL3
XSHP XSHD, V
OH4
,
PBLK, OBCLP
,
Output voltage 3
CLPDM,
V
OL4
ADCLK
Output voltage 4 CKO
Output voltage 5 MCKO
Output voltage 6
ID/EXP
,
WEN/FLD
V
OH5
V
OL5
V
OH6
V
OL6
V
OH7
V
OL7
I
OL
V1, V3A, V3B,
Output current 1 V5A, V5B, V2,
V4, V6
I
OM1
I
OM2
I
OH
Output current 2 SUB
I
OSL
I
OSH
∗
1
These input pins are Schmitt trigger inputs.
∗
2
This input pin is with pull-down register in the IC.
–5–
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
