CAT1320, CAT1321
Supervisory Circuits with
I
2
C Serial 32K CMOS
EEPROM
Description
The CAT1320 and CAT1321 are complete memory and supervisory
solutions for microcontroller−based systems. A 32 kbit serial
EEPROM memory and a system power supervisor with brown−out
protection are integrated together in low power CMOS technology.
Memory interface is via a 400 kHz I
2
C bus.
The CAT1320 provides a precision V
CC
sense circuit and drives an
open drain output, RESET low whenever V
CC
falls below the reset
threshold voltage.
The CAT1321 provides a precision VCC sense circuit that drives an
open drain output, RESET high whenever V
CC
falls below the reset
threshold voltage.
The power supply monitor and reset circuit protect memory and
system controllers during power up/down and against brownout
conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
200 ms after the supply voltage exceeds the reset threshold level. With
both active high and low reset options, interface to microcontrollers
and other ICs is simple. In addition, the RESET (CAT1320) pin can be
used as an input for push−button manual reset capability.
The CAT1320/21 memory features a 64−byte page. In addition,
hardware data protection is provided by a V
CC
sense circuit that
prevents writes to memory whenever V
CC
falls below the reset
threshold or until V
CC
reaches the reset threshold during power up.
Available packages include an 8−pin DIP, SOIC, TSSOP and
4.9 x 3 mm TDFN.
Features
♦
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PDIP−8
CASE 646AA
TSSOP−8
CASE 948S
SOIC−8
CASE 751BD
TDFN−8
CASE 511AM
ORDERING INFORMATION
For Ordering Information details, see page 13.
•
Precision Power Supply Voltage Monitor
5 V, 3.3 V and 3 V Systems
S
+5.0 V (±5%,
±10%)
S
+3.3 V (±5%,
±10%)
S
+3.0 V (±10%)
Active Low Reset, CAT1320
Active High Reset, CAT1321
Valid Reset Guaranteed at V
CC
= 1 V
400 kHz I
2
C Bus
•
•
•
•
•
•
•
•
•
•
•
•
3.0 V to 5.5 V Operation
Low Power CMOS Technology
64−Byte Page Write Buffer
1,000,000 Program/Erase Cycles
100 Year Data Retention
8−pin DIP, SOIC, TSSOP and TDFN Packages
Industrial Temperature Range
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
©
Semiconductor Components Industries, LLC, 2011
November, 2011
−
Rev. 5
1
Publication Order Number:
CAT1320/D
CAT1320, CAT1321
Table 1. THRESHOLD VOLTAGE OPTION
Part Dash
Number
−45
−42
−30
−28
−25
Minimum
Threshold
4.50
4.25
3.00
2.85
2.55
Maximum
Threshold
4.75
4.50
3.15
3.00
2.70
BLOCK DIAGRAM
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORDADDRESS
BU F F E R S
COLUMN
DECODERS
SENSEAMPS
SHIFT REGISTERS
SDA
STA RT/ STOP
LOGIC
2kbit
EEPROM
XDEC
CONTROL
LOGIC
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTROL
RESET Controller
Precision
Vcc Monitor
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
A0
A1
A2
RESET (CAT1320)
RESET (CAT1321)
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CAT1320, CAT1321
PIN CONFIGURATION
PDIP (L)
SOIC (W)
A0
1
A1
2
A2
3
TSSOP (Y)
TDFN Package 4.9 mm x 3 mm
(ZD2)
8
V
CC
CAT1320
7
RESET
6
SCL
5
SDA
8
V
CC
CAT1321
7
6
5
RESET
SCL
SDA
A0
1
A1
2
A2
3
8
V
CC
CAT1320
7
RESET
6
SCL
5
SDA
A0
A1
A2
1
2
3
4
8
7
V
CC
RESET
SCL
SDA
CAT1320
6
5
V
SS
4
V
SS
4
V
SS
A0
1
A1
2
A2
3
A0
1
A1
2
A2
3
8
CAT1321
7
6
5
V
CC
RESET
SCL
SDA
A0
A1
A2
1
2
3
4
8
7
V
CC
RESET
SCL
SDA
CAT1321
6
5
V
SS
4
V
SS
4
V
SS
PIN DESCRIPTION
RESET/RESET:
RESET OUTPUTS
These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull−down
resistor, and the RESET pin must be connected through a
pull−up resistor.
SDA:
SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
SCL:
SERIAL CLOCK
Serial clock input.
A0, A1, A2:
DEVICE ADDRESS INPUTs
When hardwired, up to eight CAT1320/21 devices may be
addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the default
values are zeros.
Table 2. PIN FUNCTION
Pin Name
RESET
V
SS
SDA
SCL
RESET
V
CC
Function
Active Low Reset Input/Output
(CAT1320)
Ground
Serial Data/Address
Clock Input
Active High Reset Output
(CAT1321)
Power Supply
Table 3. OPERATING TEMPERATURE RANGE
Industrial
−40°C
to 85°C
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3
CAT1320, CAT1321
SPECIFICATIONS
Table 4. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 seconds)
Output Short Circuit Current (Note 1)
Ratings
–40 to +85
–65 to +105
−0.5
to V
CC
+ 2.0
−0.5
to +7.0
1.0
300
100
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Output shorted for no more than one second. No more than one output shorted at a time.
Table 5. D.C. OPERATING CHARACTERISTICS
V
CC
= +3.0 V to +5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
SB
V
IL
(Note 3)
V
IH
(Note 3)
V
OL
V
OH
V
TH
Parameter
Input Leakage Current
Output Leakage Current
Power Supply Current (Write)
Power Supply Current (Read)
Standby Current
Input Low Voltage
Input High Voltage
Output Low Voltage
(SDA, RESET)
Output High Voltage
(RESET)
Reset Threshold
I
OL
= 3 mA
V
CC
= 3.0 V
I
OH
=
−0.4
mA
V
CC
= 3.0 V
CAT132x−45
(V
CC
= 5.0 V)
CAT132x−42
(V
CC
= 5.0 V)
CAT132x−30
(V
CC
= 3.3 V)
CAT132x−28
(V
CC
= 3.3 V)
CAT132x−25
(V
CC
= 3.0 V)
V
RVALID
(Note 2)
V
RT
(Note 2)
Reset Output Valid V
CC
Voltage
Reset Threshold Hysteresis
V
CC
−
0.75
4.50
4.25
3.00
2.85
2.55
1.00
15
4.75
4.50
3.15
3.00
2.70
V
mV
Test Conditions
V
IN
= GND to V
CC
V
IN
= GND to V
CC
f
SCL
= 400 kHz
V
CC
= 5.5 V
f
SCL
= 400 kHz
V
CC
= 5.5 V
V
CC
= 5.5 V
V
IN
= GND or V
CC
−0.5
0.7 x V
CC
Min
−2
−10
Typ
Max
10
10
3
1
40
0.3 x V
CC
V
CC
+ 0.5
0.4
Units
mA
mA
mA
mA
mA
V
V
V
V
V
2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
3. V
IL
min and V
IH
max are reference values only and are not tested.
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CAT1320, CAT1321
Table 6. CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V
Symbol
C
OUT
(Note 1)
C
IN
(Note 1)
Output Capacitance
Input Capacitance
Test
Test Conditions
V
OUT
= 0 V
V
IN
= 0 V
Max
8
6
Units
pF
pF
Table 7. AC CHARACTERISTICS
V
CC
= 3.0 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle
(Note 2)
Symbol
f
SCL
t
SP
t
LOW
t
HIGH
t
R
(Note 1)
t
F
(Note 1)
t
HD; STA
t
SU; STA
t
HD; DAT
t
SU; DAT
t
SU; STO
t
AA
t
DH
t
BUF
(Note 1)
t
WC
(Note 3)
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
50
1.3
5
0.6
0.6
0
100
0.6
900
1.3
0.6
300
300
Parameter
Min
Max
400
100
Units
kHz
ns
ms
ms
ns
ns
ms
ms
ns
ns
ms
ns
ns
ms
ms
1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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NXP MCU
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