9-bit Latchable Transceiver with Parity Generator/Checker
Datasheet
May 16, 2012
www.aeroflex.com/Logic
FEATURES
Latchable transceiver with output source/sink of 24mA
Option to select generate parity and check or "feed-through"
data/parity in directions A-to-B or B-to-A
Independent latch enable for A-to-B and B-to-A directions
Select pin for ODD/EVEN parity
ERRA and ERRB output pins for parity checking
Ability to simultaneously generate and check parity
m
Commercial CMOS
Operational environment:
- Total dose: 100K rad(Si)
- Single Event Latchup immune
- SEU immune
Standard Microcircuit Drawing 5962-06240
- QML compliant part
Package:
- 28-pin ceramic flatpack
PIN DESCRIPTION
Inputs
A0-A7
B0-B7
APAR, BPAR
ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
Outputs
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active LOW for
EVEN Parity
Output Enables for A or B Bus, Active Low
Select Pin for Feed-through or Generate
Mode, LOW for Generate Mode
Latch Enables for A and B Latches, HIGH
for Transparent Mode
Error Signals for Checking Generated Par-
ity with Parity In, LOW if Error Occurs
28-Lead Flatpack
Pinout
DESCRIPTION
The UT54ACTS899 is a 9-bit to 9-bit parity transceiver with
transparent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit data
busses in either direction. The UT54ACTS899 features inde-
pendent latch enables for the A-to-B direction and the B-to-A
direction, a select pin for ODD/EVEN parity, and separate
error signal output pins for checking parity.
ODD/EVEN
ERRA
LEA
A0
A1
A2
A3
A4
A5
A6
A7
APAR
GBA
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
GAB
B0
B1
B2
B3
B4
B5
B6
B7
BPAR
LEB
SEL
ERRB
1
LOGIC DIAGRAM
OE
(27) GAB
9-bit
Transparent
Latch
9-bit
Output
Buffer
LEA
A0
A1
A2
(3)
(4)
(5)
(6)
LE
Parity
Generator
1
mux
0
(26)
(25)
(24)
(23)
(22)
(21)
(20)
(19)
B0
B1
B2
B3
B4
B5
B6
B7
A3 (7)
A4 (8)
A5 (9)
A6 (10)
A7 (11)
APAR (12)
(18) BPAR
9-bit
Output
Buffer
9-bit
Transparent
Latch
GBA (13)
(17)
OE
1
mux
0
LEB
LE
SEL (16)
Parity
Generator
(2) ERRA
(15) ERRB
ODD/EVEN (1)
2
FUNCTIONAL DESCRIPTION
The UT54ACTS899 has three principal modes of operation
which are outlined below. These modes apply to both A-to-B
and B-to-A directions.
- Bus A (B) communicates to Bus B (A), parity is generated
and passed on to the B (A) Bus as BPAR (APAR). If LEB
(LEA) is HIGH and the Mode Select (SEL) is LOW, the parity
generated from B[0:7] (A[0:7]) can be checked and moni-
tored by ERRB (ERRA).
- Bus A (B) communicates to Bus B (A) in a feed-through mode
if SEL is HIGH. Parity is still generated and checked as
ERRA and ERRB in the feed-through mode (can be used as
an interrupt to signal a data/parity bit error to the CPU).
- Independent Latch Enables (LEA and LEB) allow other per-
mutations of generating/checking. (see Function Table below)
FUNCTIONAL TABLE
INPUTS
GAB
H
GBA
H
SEL
X
LEA
X
LEB
X
Busses A and B are Tri-State (input A & B simultaneously)
O
PERATION
H
L
L
L
H
Generates parity from B[0:7] based on O/E (Note 1). Generated parity
-->
APAR.
Generated parity checked against BPAR and output as ERRB.
Generates parity from B[0:7] based on O/E. Generated parity --> APAR.
Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check as ERRA.
Generates parity from B latch data based on O/E. Generated parity --> APAR.
Generated parity checked against latched BPAR and output as ERRB.
BPAR/B[0:7] --> APAR/A[0:7] Feed-through mode.
Generated parity checked against BPAR and output as ERRB.
BPAR/B[0:7] --> APAR/A[0:7] Feed-through mode.
Generated parity checked against BPAR and output as ERRB.
APAR/A[0:7] fed back through the A latch for generate/check as ERRA.
Generates parity from A[0:7] based on O/E. Generated parity --> BPAR.
Generated parity checked against APAR and output as ERRA.
Generates parity from A[0:7] based on O/E. Generated parity --> BPAR.
Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check as ERRB.
Generates parity from A latch data based on O/E. Generated parity --> BPAR.
Generated parity checked against latched APAR and output as ERRA.
APAR/A[0:7)]--> BPAR/B[0:7] Feed-through mode.
Generated parity checked against APAR and output as ERRA.
APAR/A[0:7] --> BPAR/B[0:7] Feed-through mode.
Generated parity checked against APAR and output as ERRA.
BPAR/B[0:7] fed back through the B latch for generate/check as ERRB.
Output to A bus and B bus (NOT ALLOWED).
H
L
L
H
H
H
L
L
X
L
H
L
H
X
H
H
L
H
H
H
L
H
L
H
L
L
H
L
H
H
L
H
L
L
X
L
H
H
H
L
L
H
H
H
H
L
L
X
X
X
H = High voltage level
L = Low voltage level
X = Do not care
Note 1: O/E = ODD/EVEN
3
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEU Onset LET
SEL Immune
Neutron Fluence
2
LIMIT
1.0E5
>108
>108
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
DD
V
I/O
T
STG
T
J
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin during operation
Storage Temperature range
Maximum junction temperature
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 6.0
-0.3 to V
DD
+0.3
-65 to +150
+175
20
+10
UNITS
V
V
C
C
C/W
mA
mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
t
INRISE
t
INFALL
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
Maximum input rise or fall time
(V
IN
transitioning between V
IL
(max) and V
IH
(min))
LIMIT
4.5 to 5.5
0 to V
DD
-55 to +125
20
UNITS
V
V
o
C
ns
4
DC ELECTRICAL CHARACTERISTICS*
1
( VDD = 3.3 + 0.3V, T
C
= -55C to +125C); Unless otherwise noted, Tc is per the temperature ordered
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