®
HI-574A, HI-674A
Data Sheet
August 7, 2008
FN3096.6
Complete, 12-Bit A/D Converters with
Microprocessor Interface
The HI-X74(A) is a complete 12-bit, Analog-to-Digital
Converter, including a +10V reference clock, three-state
outputs and a digital interface for microprocessor control.
Successive approximation conversion is performed by two
monolithic dice housed in a 28 lead package. The bipolar
analog die features the Intersil Dielectric Isolation process,
which provides enhanced AC performance and freedom
from latch-up.
Custom design of each IC (bipolar analog and CMOS digital)
has yielded improved performance over existing versions of
this converter. The voltage comparator features high PSRR
plus a high speed current-mode latch, and provides precise
decisions down to 0.1 LSB of input overdrive. More than 2X
reduction in noise has been achieved by using current
instead of voltage for transmission of all signals between the
analog and digital ICs. Also, the clock oscillator is current
controlled for excellent stability over temperature.
The HI-X74(A) offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and offset
accuracy. The low noise buried zener reference circuit is
trimmed for minimum temperature coefficient.
Power requirements are +5V and ±12V to ±15V, with typical
dissipation of 385mW (HI-574A, HI-674A) at 12V.
Features
• Complete 12-Bit A/D Converter with Reference and Clock
• Full 8-Bit, 12-Bit or 16-Bit Microprocessor Bus Interface
• Bus Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns
• No Missing Codes Over Temperature
• Minimal Setup Time for Control Signals
• Fast Conversion Times
- HI-574A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25µs
- HI-674A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15µs
• Low Noise, via Current-Mode Signal Transmission
Between Chips
• Byte Enable/Short Cycle (A
O
Input)
- Guaranteed Break-Before-Make Action, Eliminating Bus
Contention During Read Operation. Latched by Start
Convert Input (To Set the Conversion Length)
• Supply Voltage . . . . . . . . . . . . . . . . . . . . . . ±12V to ±15V
• Pb-Free Available (RoHS Compliant)
Applications
• Military and Industrial Data Acquisition Systems
• Electronic Test and Scientific Instrumentation
• Process Control Systems
Pinout
HI-574A, HI-674A
(28 LD PDIP, SBDIP)
TOP VIEW
+5V SUPPLY, V
LOGIC
DATA MODE SEL, 12/8
CHIP SEL, CS
BYTE ADDR/SHORT
CYCLE, A
O
READ/CONVERT, R/C
CHIP ENABLE, CE
+12V/+15V SUPPLY, V
CC
+10V REF, REF OUT
ANALOG
COMMON, AC
1
2
3
4
5
6
7
8
9
28 STATUS, STS
27 DB11
26 DB10
25 DB9
24 DB8
23 DB7
22 DB6
21 DB5
20 DB4
19 DB3
18 DB2
17 DB1
16 DB0
LSB
DIGITAL
DATA
OUTPUTS
MSB
REFERENCE INPUT 10
-12V/-15V SUPPLY, V
EE
11
BIPOLAR OFFSET 12
BIP OFF
10V INPUT 13
20V INPUT 14
15 DIG COMMON,
DC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI-574A, HI-674A
Ordering Information
PART NUMBER
HI3-574AJN-5
PART MARKING
HI3-574AJN-5
INL
±1.0 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±1.0 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±0.5 LSB
±0.5 LSB
TEMPERATURE RANGE
(°C)
0 to +75
0 to +75
0 to +75
0 to +75
0 to +75
0 to +75
-55 to +125
-55 to +125
0 to +75
0 to +75
0 to +75
0 to +75
0 to +75
-55 to +125
PACKAGE
28 Ld PDIP
28 Ld PDIP (Pb-Free)
28 Ld PDIP
28 Ld PDIP (Pb-Free)
28 Ld SBDIP (Pb-Free)
28 Ld SBDIP (Pb-Free)
28 Ld SBDIP (Pb-Free)
28 Ld SBDIP (Pb-Free)
28 Ld PDIP
28 Ld PDIP (Pb-Free)
28 Ld PDIP
28 Ld PDIP (Pb-Free)
28 Ld SBDIP (Pb-Free)
28 Ld SBDIP (Pb-Free)
PKG.
DWG. #
E28.6
E28.6
E28.6
E28.6
D28.6
D28.6
D28.6
D28.6
E28.6
E28.6
E28.6
E28.6
D28.6
D28.6
HI3-574AJN-5Z (Notes 1, 3) HI3-574AJN-5Z
HI3-574AKN-5
HI3-574AKN-5
HI3-574AKN-5Z (Notes 1, 3) HI3-574AKN-5Z
HI1-574AJD-5 (Note 2)
HI1-574AKD-5 (Note 2)
HI1-574ASD-2 (Note 2)
HI1-574ATD-2 (Note 2)
HI3-674AJN-5
HI1-574AJD -5
HI1-574AKD -5
HI1-574ASD -2
HI1- 574ATD-2
HI3-674AJN-5
HI3-674AJN-5Z (Notes 1, 3) HI3-674AJN-5Z
HI3-674AKN-5
HI3-674AKN-5
HI3-674AKN-5Z (Notes 1, 3) HI3-674AKN-5Z
HI1-674AKD-5 (Note 2)
HI1-674ATD/883 (Note 2)
NOTES:
HI1-674AKD -5
HI1-674ATD /883
1. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
2
FN3096.6
August 7, 2008
HI-574A, HI-674A
Functional Block Diagram
BIT OUTPUTS
MSB
LSB
12/8
CS
A
O
R/C
CE
CONTROL
LOGIC
NIBBLE A (NOTE)
NIBBLE B (NOTE)
NIBBLE C (NOTE)
THREE-STATE BUFFERS AND CONTROL
V
LOGIC
POWER-UP RESET
12 BITS
DIGITAL
COMMON
STS
CLK
OSCILLATOR
SAR
STROBE
DIGITAL CHIP
ANALOG CHIP
12 BITS
V
CC
V
EE
V
REF
IN
10k
V
REF
OUT
DAC
-
COMP
+
5k
+10V
REF
+
-
5k
10k
5k
2.5k
ANALOG
COMMON
BIP
OFF
20V
10V
INPUT INPUT
NOTE: “Nibble” is a 4-bit digital word.
3
FN3096.6
August 7, 2008
HI-574A, HI-674A
Absolute Maximum Ratings
Supply Voltage
V
CC
to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +16.5V
V
EE
to Digital Common . . . . . . . . . . . . . . . . . . . . . . . 0V to -16.5V
V
LOGIC
to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +7V
Analog Common to Digital Common . . . . . . . . . . . . . . . . . . . .±1V
Control Inputs
(CE, CS, A
O
, 12/8, R/C) to Digital Common . . -0.5V to V
LOGIC
+0.5V
Analog Inputs
(REFIN, BIPOFF, 10VIN) to Analog Common . . . . . . . . . . ±16.5V
20VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . . . . . ±24V
REFOUT . . . . .Indefinite Short To Common, Momentary Short To V
CC
Thermal Information
Thermal Resistance (Typical, Note 4)
θ
JA
(°C/W)
θ
JC
(°C/W)
SBDIP Package . . . . . . . . . . . . . . . . . .
55
18
PDIP Package* . . . . . . . . . . . . . . . . . . .
60
N/A
Maximum Junction Temperature
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Maximum Storage Temperature Range
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range
HI3-574Axx-5, HI1-674Axx-5 . . . . . . . . . . . . . . . . . . 0°C to +75°C
HI1-574AxD-2, HI1-674AxD-2 . . . . . . . . . . . . . . .-55°C to +125°C
Die Characteristics
Transistor Count
HI-574A, HI-674A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
4.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC and Transfer Accuracy Specifications
Typical at +25°C with V
CC
= +15V or +12V, V
LOGIC
= +5V, V
EE
= -15V or -12V;
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not
production tested.
TEMPERATURE RANGE
-5 (0°C to +75°C)
PARAMETER
DYNAMIC CHARACTERISTICS
Resolution (Max)
Linearity Error
+25°C (Max)
0°C to +75°C (Max)
Max Resolution For Which No Missing Codes Is Guaranteed
+25°C
T
MIN
to T
MAX
Unipolar Offset (Max)
Adjustable to Zero
Bipolar Offset (Max)
V
IN
= 0V (Adjustable to Zero)
V
IN
= -10V
Full Scale Calibration Error
+25°C (Max), With Fixed 50Ω Resistor From REF OUT To REF IN
(Adjustable to Zero)
T
MIN
to T
MAX
(No Adjustment At +25°C)
T
MIN
to T
MAX
(With Adjustment To Zero +25°C)
±0.25
±0.475
±0.22
±0.25
±0.375
±0.12
% of FS
% of FS
% of FS
±4
±0.15
±4
±0.1
LSB
% of FS
±2
±1.5
LSB
12
11
12
12
Bits
Bits
±1
±1
±
1
/
2
±
1
/
2
LSB
LSB
12
12
Bits
J SUFFIX
K SUFFIX
UNITS
4
FN3096.6
August 7, 2008
HI-574A, HI-674A
DC and Transfer Accuracy Specifications
Typical at +25°C with V
CC
= +15V or +12V, V
LOGIC
= +5V, V
EE
= -15V or -12V;
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not
production tested.
(Continued)
TEMPERATURE RANGE
-5 (0°C to +75°C)
PARAMETER
Temperature Coefficients
Guaranteed Max Change, T
MIN
to T
MAX
(Using Internal Reference)
Unipolar Offset
Bipolar Offset
Full Scale Calibration
Power Supply Rejection Max Change In Full Scale Calibration
+13.5V < V
CC
< +16.5V or +11.4V < V
CC
< +12.6V
+4.5V < V
LOGIC
< +5.5V
-16.5V < V
EE
< -13.5V or -12.6V < V
EE
< -11.4V
ANALOG INPUTS
Input Ranges
Bipolar
-5 to +5 (Note 6)
-10 to +10 (Note 7)
Unipolar
0 to +10 (Note 6)
0 to +20 (Note 7)
Input Impedance
10V Span
20V Span
POWER SUPPLIES
Operating Voltage Range
V
LOGIC
V
CC
V
EE
Operating Current
I
LOGIC
I
CC
+15V Supply
I
EE
-15V Supply
Power Dissipation
±15V, +5V
±12V, +5V
Internal Reference Voltage
T
MIN
to T
MAX
Output Current, Available For External Loads (External Load Should Not
Change During Conversion).
+10.00 ±0.05 Max
2.0 Max
V
mA
515 Typ, 720 Max
385 Typ
mW
mW
7 Typ, 15 Max
11 Typ, 15 Max
21 Typ, 28 Max
mA
mA
mA
+4.5 to +5.5
+11.4 to +16.5
-11.4 to -16.5
V
V
V
5k, ±25%
10k, ±25%
Ω
Ω
V
V
V
V
±2
±
1
/
2
±2
±1
±
1
/
2
±1
LSB
LSB
LSB
±2
±2
±9
±1
±1
±2
LSB
LSB
LSB
J SUFFIX
K SUFFIX
UNITS
5
FN3096.6
August 7, 2008
FPGA/CPLD
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