CMCPCI102B
CompactPCI
®
Backplane Interface
Features
•
•
•
•
•
•
•
•
•
CompactPCI® standards compliant
Allows CompactPCI System Cards to be
used in any Slot
Provides termination for up to ten channels
Provides a series switch in each channel
Supports hot-swap capability
Very low capacitance load on each line
Industrial temperature range
28-pin TSSOP package
Lead-free version available
Product Description
The CMCPCI102BT/BR is a 10-channel backplane
interface/termination IC specifically designed for Com-
pactPCI
redundant
system-slot
cards.
The
CMCPCI102BT/BR allows CompactPCI boards to
interface to the backplane and provides the versatility
to use system cards in any slot (system or peripheral).
Per the CompactPCI specification, the CMCPCI102BT/
BR provides a 10Ω termination resistor for each chan-
nel to terminate the transmission line stub on the
board. An integral series switch and associated control
signal (SW_EN) permits connection/disconnection of
the channel, so that the device side of the circuit may
be isolated from the backplane side.
The CompactPCI standard requires system boards to
be hot-swappable. To accommodate this requirement,
the CMCPCI102BT/BR features a switched 10kΩ resis-
tor connected to the 1V Precharge Supply Voltage. If
the precharge enable pin (P_EN) is asserted, then the
10kΩ pull-up resistors are connected to precharge the
circuits.
In addition, a system board requirement mandates
either a 1.0kΩ pull-up resistor or a 2.7kΩ resistor con-
nected to VIO. CompactPCI slot cards must work in
either 3.3V or 5V systems, hence the need for both
2.7kΩ and 1kΩ resistors. If the 3_EN pin is logic high,
the 2.7kΩ resistor is used as the pull-up. If the 5_EN pin
is logic high, the 1kΩ resistor is used.
The CMCPCI102BT/BR integrates all these functions in
a low-profile 28-pin TSSOP package and is available
with optional lead-free finishing.
Applications
•
•
•
•
•
•
•
Redundant System CompactPCI® cards
Hot-swap CompactPCI cards
Industrial PCs
Telecom/Datacom equipment
Instrumentation
Computer Telephony
Real-time machine control
Simplified Electrical Schematic
1V
For all Enable signals:
Logic 0 = switch open
Logic 1 = switch closed
*One of 10 parallel
channels is shown.
VIO
3_EN
5_EN
SW_EN
SW
PU1
SW
PU2
SW
PU3
P_EN
R
PU1
10kΩ
R
PU2
2.7kΩ
R
S
SW
S
R
PU3
1kΩ
A1-A10*
Backplane Side
10Ω
CompactPCI Device Side
B1-B10*
©
2005 California Micro Devices Corp. All rights reserved.
02/28/05
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
1
CMCPCI102B
PACKAGE / PINOUT DIAGRAM
Top View
A1
A2
A3
A4
A5
1V
P_EN
GND
CAP
A6
A7
A8
A9
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
B1
B2
B3
B4
B5
VIO
5_EN
3_EN
SW_EN
B6
B7
B8
B9
B10
Note: This drawing is not to scale.
28-pin TSSOP
PIN DESCRIPTIONS
PIN(S)
1-5
10-14
24-28
15-19
6
7
8
9
20
NAME
A1 - A5
A6 - A10
B1 - B5
B6 - B10
1V
P_EN
GND
CAP
SW_EN
DESCRIPTION
The backplane-side input signals for channels 1 through 5, respectively.
The backplane-side input signals for channels 6 through 10, respectively.
The device-side connection for channels 1 through 5, respectively.
The device-side connection for channels 6 through 10, respectively.
A precharge supply voltage input for all channels. This voltage can be less than or equal to VIO.
The precharge enable input which controls the precharge pull-up resistors. When this active high
control signal is set to ’1’, the precharge of all channels is enabled.
The ground voltage reference for the CMCPCI102BT/BR.
A capacitor must be placed from this pin to GND. The recommended value is 0.01µF,16V.
The series switch enable input. When this active high control signal is set to ’1’, the series switch
between the channel’s backplane-side terminal and device-side terminal is closed. When this sig-
nal is cleared to ’0’, the switch is open.
The enable signal for the device-side channel pull-up mechanism when 3.3V is the supply volt-
age. When this active high control signal is set to ’1’, the 2.7kΩ pull-up resistor which pulls up the
channel to the supply rail is engaged. Otherwise, this pin should be set to ’0’.
The enable signal for the device-side channel pull-up mechanism when 5V is the supply voltage.
When this active high control signal is set to ’1’, the 1kΩ pull-up resistor which pulls up the channel
to the supply rail is engaged. Otherwise, this pin should be set to ’0’.
The positive supply voltage for the CMCPCI102BT/BR. Either 3.3V or 5V may be used.
21
3_EN
22
5_EN
23
VIO
©
2005 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
02/28/05
CMCPCI102B
Ordering Information
PART NUMBERING INFORMATION
Standard Finish
Pins
28
Package
TSSOP
Ordering Part
Number
1
CMCPCI102BT
Part Marking
CPCI102B
Lead-free Finish
Ordering Part
Number
1
CMCPCI102BR
Part Marking
CPCI102BR
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VIO (supply voltage)
Pin Voltages
1V, P_EN, 3_EN, 5_EN, SW_EN
A1-A10
B1-B10
ESD Withstand Voltage
Human Body Model, MIL-STD-883D, Method 3015 (Notes 1, 2)
Storage Temperature Range
Operating Temperature Range (Ambient)
DC Power per Resistor
Package Power Rating
RATING
-0.5 to +6
-0.5 to (VIO+0.5)
-0.5 to (VIO+0.5)
-0.5 to (VIO+0.5)
+2000
-65 to +150
-40 to +85
62
1
UNITS
V
V
V
V
V
°C
°C
mW
W
Note 1: ESD is applied to input / output pins with respect to GND, one at a time; unused pins are left open.
Note 2: This parameter guaranteed by design.
STANDARD OPERATING CONDITIONS
PARAMETER
VIO (supply voltage)
Pin Voltages
P_EN, 3_EN, 5_EN, SW_EN, 1V
A1-A10
B1-B10
Ambient Operating Temperature Range
RATING
3 to 5.5
0 to VIO
0 to VIO
0 to VIO
-40 to +85
UNITS
V
V
V
V
°C
©
2005 California Micro Devices Corp. All rights reserved.
02/28/05
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
3
CMCPCI102B
Specifications (Cont’d)
ELECTRICAL OPERATING CHARACTERISTICS
(NOTE 1)
SYMBOL
R
S1
R
S2
R
PU1
TOL
RPU2
TOL
RPU3
TCR
PU
C
1
C
2
PARAMETER
Series Resistance through R
S
Series Resistance through R
S
Resistance of R
PU1
pull-up
Resistance Tolerance
(R
PU2
and R
PU3
)
Temperature Coefficient of
Resistance (R
PU1
, R
PU2
, R
PU3
)
Capacitance on backplane side
(A side) of series resistor R
S
Capacitance on device side (B
side) of series resistor R
S
and
series switch SW
S
Logic Low Input Voltage to P_EN,
3_EN, 5_EN, SW_EN
Logic High Input Voltage to P_EN,
3_EN, 5_EN, SW_EN
Leakage Current into P_EN, 3_EN,
5_EN, SW_EN
Supply Current for internal circuits
(measured at GND pin)
Switch SW
S
closure delay from the
low-to-high transition of SW_EN
Note 2, ’CAP’ pin capaci-
tor=0.01µF
GND < V < VIO
Measured @ 66MHz,
0VDC, SW_EN=0V; Note 2
Measured @ 66MHz,
0VDC, VIO=5V, 5_EN=5V
SW_EN=0V; Note 2
-0.5
[VIO] x 0.7
+1
0.25
14
12
10
CONDITIONS
A to B; switch SW
S
closed;
T
A
=25°C
A to B; switch SW
S
open;
T
A
=25°C
T
A
=25°C
T
A
=25°C
MIN
5
1
9.5
18
+5
TYP
10
MAX
15
UNITS
Ω
MΩ
kΩ
%
-100
1.9
4.2
ppm/°C
pF
pF
V
IL
V
IH
I
LEAK
I
GND
t
PLH
t
PHL
t
PPU
[VIO] x 0.3
[VIO] + 0.5
+10
1
V
V
µA
mA
ms
µs
ns
Switch SW
S
delay from the high-to- Note 2, ’CAP’ pin capaci-
tor=0.01µF
low transition of SW_EN
Propagation delay for pull-up
switches SW
PU1
, SW
PU2
, and
SW
PU3
, all transitions
Note 2
Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified.
Note 2: This parameter is guaranteed by design; it is not tested 100%.
©
2005 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
02/28/05
CMCPCI102B
Performance Information
CAP Pin Capacitance
Resistance Variation with Input Voltage
The series resistance R
S
varies with input voltage and
supply voltage, as shown in
Figure 1.
Variation of 10R Resistor with I/O Voltage, T=25'C
15
14
13
12
Vcc5.5
Vcc3.0
Some external capacitance is necessary to prevent the
voltage on the CAP pin from falling during sustained
data transfers through the device. This ensures that
the logic 1 level does not degrade.
The time required to open and close the series switch,
SWs, varies according to how much capacitance is
present on the CAP pin.
The minimum usable value is 200pF, placed close to
the pins. A 0.01uF, 16V capacitor is recommended.
See
Figure 3
and
Figure 4
for variation of switch on/off
times vs. capacitance.
Switch ON Time vs. CAP Capacitor Value
16
Resistance [
Ω
]
11
10
9
8
7
6
5
0
1
2
3
I/O Voltage [ V ]
4
5
6
14
12
Figure 1. Resistance Variation vs. Input Voltage
SWs Closing Tim e [mS]
10
8
6
4
2
0
0
2000
4000
6000
8000
10000
12000
Capacitor Value on CAP Pin [pF]
Resistance Variation with Temperature
The series resistance R
S
also varies with temperature,
as shown in
Figure 2.
Temperature Variation of 10R Resistor
15
14
13
12
V
CC
5V
IN
0
V
CC
5V
IN
5
V
CC
3V
IN
0
V
CC
3V
IN
3
Figure 3. Switch ON Time vs. CAP Capacitor Value
Switch OFF Time vs. CAP Capacitor Value
14
12
10
8
Resistance [
Ω
]
11
10
9
8
7
6
5
-40
-20
0
20
40
60
80
100
SWs Opening Tim e [
µ
S]
Temperature [
o
C ]
6
4
2
0
0
2000
4000
6000
8000
10000
12000
Capacitor Value on CAP Pin [pF]
CONDITIONS:
Curve V
CC
3V
IN
0:
Curve V
CC
3V
IN
3:
Curve V
CC
5V
IN
0:
Curve V
CC
5V
IN
5:
V
IO
= 3.0V
V
IO
= 3.0V
V
IO
= 5.5V
V
IO
= 5.5V
channel voltage = 0.0V
channel voltage = 3.0V
channel voltage = 0.0V
channel voltage = 5.5V
Figure 2. Resistance Variation vs. Temperature
Figure 4. Switch OFF Time vs. CAP Capacitor Value
©
2005 California Micro Devices Corp. All rights reserved.
02/28/05
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
5
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