CED6060R/CEU6060R
Feb. 2003
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
6
60V , 30A , R
DS(ON)
=25m
Ω
@V
GS
=10V.
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handling capability.
TO-251 & TO-252 package.
D
G
S
G
D
S
D
G
CEU SERIES
TO-252AA(D-PAK)
CED SERIES
TO-251(l-PAK)
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous @T
J
=125 C
-Pulsed
Drain-Source Diode Forward Current
Maximum Power Dissipation
@Tc=25 C
Derate above 25 C
Operating and Storage Temperature Range
Symbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
STG
Limit
60
20
30
120
30
50
0.3
-55 to 175
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
R
JC
R
JA
6-42
3
50
C/W
C/W
CED6060R/CEU6060R
ELECTRICAL CHARACTERISTICS (T
C
=25 C unless otherwise noted)
Parameter
Single Pulse Drain-Source
Avalanche Energy
Maximum Drain-Source
Avalanche Current
Symbol
a
Condition
V
DD
=25V, L = 25µH
R
G
=
25
Ω
Min Typ Max Unit
DRAIN-SOURCE AVALANCHE RATING
E
AS
I
AS
200
30
mJ
A
6
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate-Body Leakage
BV
DSS
I
DSS
I
GSS
V
GS(th)
R
DS(ON)
I
D(ON)
g
FS
b
V
GS
= 0V, I
D
= 250µA
V
DS
= 60V, V
GS
= 0V
V
GS
= 20V, V
DS
= 0V
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10V, I
D
= 24A
V
GS
= 10V, V
DS
= 10V
V
DS
= 10V, I
D
= 24A
V
DD
= 30V,
I
D
= 30A,
V
GS
= 10V,
R
GEN
= 7.5Ω
60
25
V
µA
100 nA
ON CHARACTERISTICS
a
Gate Threshold Voltage
Drain-Source On-State Resistance
On-State Drain Current
Forward Transconductance
2
4
25
60
20
15
45
36
V
DS
=48V, I
D
= 30A,
V
GS
=10V
6-43
V
mΩ
A
S
SWITCHING CHARACTERISTICS
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
t
D(ON)
t
r
t
D(OFF)
t
f
Q
g
Q
gs
Q
gd
20
60
43
ns
ns
ns
ns
nC
nC
nC
250 300
130 150
9
19
CED6060R/CEU6060R
ELECTRICAL CHARACTERISTICS (T
C
=25 C unless otherwise noted)
Parameter
DYNAMIC CHARACTERISTICS
b
Input Capacitance
C
ISS
C
OSS
C
RSS
Symbol
Condition
Min Typ Max Unit
1178
428
95
P
F
P
F
P
F
6
Output Capacitance
Reverse Transfer Capacitance
V
DS
=25V, V
GS
= 0V
f =1.0MH
Z
DRAIN-SOURCE DIODE CHARACTERISTICS
b
Diode Forward Voltage
V
SD
V
GS
= 0V, Is =24A
0.9
1.3
V
Notes
a.Pulse Test:Pulse Width 300 s, Duty Cycle 2%.
b.Guaranteed by design, not subject to production testing.
40
V
GS
=10,8,7V
35
6V
40
T
J
=125 C
25 C
30
I
D
, Drain Current(A)
25
V
GS
=5V
20
15
10
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
4V
I
D
, Drain Current (A)
30
20
10
-55 C
0
2
3
4
5
6
7
8
V
DS
, Drain-to-Source Voltage (V)
V
GS
, Gate-to-Source Voltage (V)
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
6-44
CED6060R/CEU6060R
1800
3.0
R
DS(ON)
, Normalized
Drain-Source On-Resistance
V
GS
=10V
2.5
2.0
Tj=125 C
1.5
25 C
1.0
0.5
0
-55 C
1500
C, Capacitance (pF)
1200
900
600
Ciss
Coss
300
Crss
0
0
10
15
20
25
30
0
10
20
30
40
50
6
V
DS
, Drain-to Source Voltage (V)
I
D
, Drain Current(A)
Figure 3. Capacitance
Figure 4. On-Resistance Variation with
Drain Current and Temperature
BV
DSS
, Normalized
Drain-Source Breakdown Voltage
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-50 -25
I
D
=250 A
Vth, Normalized
Gate-Source Threshold Voltage
1.15
1.10
1.05
1.0
0.95
0.90
0.85
0.80
-50 -25
0
25 50
75 100 125 150
V
DS
=V
GS
I
D
=250 A
0
25
50
75 100 125 150
Tj, Junction Temperature ( C)
Tj, Junction Temperature ( C)
Figure 5. Gate Threshold Variation
with Temperature
50
Figure 6. Breakdown Voltage Variation
with Temperature
100
g
FS
, Transconductance (S)
30
20
10
V
DS
=10V
0
0
10
20
30
40
Is, Source-drain current (A)
40
10
1
0.4
0.6
0.8
1.0
1.2
1.4
I
DS
, Drain-Source Current (A)
V
SD
, Body Diode Forward Voltage (V)
Figure 7. Transconductance Variation
with Drain Current
6-45
Figure 8. Body Diode Forward Voltage
Variation with Source Current
CED6060R/CEU6060R
15
V
GS
, Gate to Source Voltage (V)
300
I
D
, Drain Current (A)
12
9
6
3
0
0
V
DS
=48V
I
D
=30A
100
R
D
O
S
(
L
N)
im
it
10
1m
10
0
10
s
s
s
10
V
GS
=10V
Single Pulse
Tc=25 C
10
DC
ms
0m
s
6
1
6
12 18
24 30
36
42
48
1
10
60 100
Qg, Total Gate Charge (nC)
V
DS
, Drain-Source Voltage (V)
Figure 9. Gate Charge
Figure 10. Maximum Safe
Operating Area
V
DD
t
on
V
IN
D
V
GS
R
GEN
G
90%
t
off
t
r
90%
R
L
V
OUT
t
d(on)
V
OUT
t
d(off)
90%
10%
t
f
10%
INVERTED
S
V
IN
50%
10%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
2
r(t),Normalized Effective
Transient Thermal Impedance
1
D=0.5
0.2
0.1
0.1
0.05
0.02
0.01
Single Pulse
0.01
0.01
P
DM
t
1
t
2
1. R
JA
(t)=r (t) * R
JA
2. R
JA
=See Datasheet
3. T
JM-
T
A
= P
DM
* R
JA
(t)
4. Duty Cycle, D=t1/t2
1
10
100
1000
10000
0.1
Square Wave Pulse Duration (msec)
Figure 13. Normalized Thermal Transient Impedance Curve
6-46
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