CEP06N5/CEB06N5
Oct. 2002
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
500V , 6.6A , R
DS(ON)
=1
Ω
@V
GS
=10V.
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handling capability.
TO-220 & TO-263 package.
4
4
D
G
D
G
G
D
S
S
CEB SERIES
TO-263(DD-PAK)
CEP SERIES
TO-220
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
-Pulsed
Drain-Source Diode Forward Current
Maximum Power Dissipation
@Tc=25 C
Derate above 25 C
Operating and Storage Temperautre Range
Symbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
STG
Limit
500
30
6.6
20
6.6
104
0.83
-55 to 150
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
R
JC
R
JA
4-17
1.2
62.5
C/W
C/W
CEP06N5/CEB06N5
ELECTRICAL CHARACTERISTICS (T
C
=25 C unless otherwise noted)
4
4
Parameter
Single Pulse Drain-Source
Avalanche Energy
Maximum Drain-Source
Avalanche Current
Symbol
a
Condition
V
DD
=50V, L=24mH
R
G
=25Ω
Min Typ Max Unit
DRAIN-SOURCE AVALANCHE RATING
E
AS
I
AS
500
6
mJ
A
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate-Body Leakage
BV
DSS
I
DSS
I
GSS
V
GS(th)
R
DS(ON)
I
D(ON)
g
FS
b
V
GS
= 0V,I
D
= 250µA
V
DS
= 500V, V
GS
= 0V
V
GS
= 30V, V
DS
= 0V
V
DS
= V
GS
, I
D
= 250µA
V
GS
=10V, I
D
= 4A
V
GS
= 10V, V
DS
= 10V
V
DS
= 50V, I
D
= 4A
V
DD
=250V,
I
D
= 6A,
V
GS
= 10V
R
GEN
=18
Ω
500
25
V
µA
100 nA
ON CHARACTERISTICS
a
Gate Threshold Voltage
Drain-Source On-State Resistance
On-State Drain Current
Forward Transconductance
2
4
0.85
1.0
6
4
23
35
44
54
V
DS
=400V, I
D
= 6A,
V
GS
=10V
4-18
V
Ω
A
S
SWITCHING CHARACTERISTICS
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
t
D(ON)
t
r
t
D(OFF)
t
f
Q
g
Q
gs
Q
gd
45
70
90
65
ns
ns
ns
ns
nC
nC
nC
162 240
9
27
CEP06N5/CEB06N5
ELECTRICAL CHARACTERISTICS (T
C
=25 C unless otherwise noted)
Parameter
DYNAMIC CHARACTERISTICS
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Diode Forward Voltage
C
ISS
C
OSS
C
RSS
V
SD
V
GS
= 0V, Is =6A
V
DS
=25V, V
GS
= 0V
f =1.0MH
Z
823
110
64
1.5
P
F
P
F
P
F
Symbol
Condition
Min Typ Max Unit
4
4
DRAIN-SOURCE DIODE CHARACTERISTICS
a
V
Notes
a.Pulse Test:Pulse Width 300 s, Duty Cycle 2%.
b.Guaranteed by design, not subject to production testing.
12
V
GS
=10,9,8,7V
10
10
I
D
, Drain Current(A)
8
V
GS
=6V
6
4
I
D
, Drain Current (A)
150 C
1
V
GS
=5V
2
0
0
2
4
6
8
10
12
-55 C
0.1
2
25 C
1.V
DS
=40V
2.Pulse Test
4
6
8
10
V
GS
, Gate-to-Source Voltage (V)
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
4-19
CEP06N5/CEB06N5
R
DS(ON)
, Normalized
R
DS(ON)
,
On-Resistance(Ohms)
1200
1000
2.2
1.9
1.6
1.3
1.0
0.7
0.4
-100
-50
0
50
100
150
200
I
D
=4
V
GS
=10V
C, Capacitance (pF)
4
4
Ciss
800
600
400
200
0
0
5
10
15
20
25
Coss
Crss
V
DS
, Drain-to Source Voltage (V)
T
J
, Junction Temperature( C)
Figure 3. Capacitance
BV
DSS
, Normalized
Drain-Source Breakdown Voltage
Vth, Normalized
Gate-Source Threshold Voltage
1.30
1.20
1.10
1.0
0.90
0.80
0.70
0.60
-50 -25
0
25
50
75 100 125 150
V
DS
=V
GS
I
D
=250 A
Figure 4. On-Resistance Variation with
Temperature
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-50 -25
I
D
=250 A
0
25
50
75 100 125 150
Tj, Junction Temperature ( C)
Tj, Junction Temperature ( C)
Figure 5. Gate Threshold Variation
with Temperature
4
Figure 6. Breakdown Voltage Variation
with Temperature
20
10
V
GS
=0V
g
FS
, Transconductance (S)
V
DS
=50V
3
2
Is, Source-drain current (A)
0
1
2
3
4
1
1
0
0.1
0.4
0.6
0.8
1.0
1.2
I
DS
, Drain-Source Current (A)
V
SD
, Body Diode Forward Voltage (V)
Figure 7. Transconductance Variation
with Drain Current
4-20
Figure 8. Body Diode Forward Voltage
Variation with Source Current
CEP06N5/CEB06N5
V
GS
, Gate to Source Voltage (V)
15
12
9
6
3
0
0
20
40
60
80
Qg, Total Gate Charge (nC)
10
V
DS
=400V
I
D
=6A
I
D
, Drain Current (A)
0
s
10
1
1m
s
10
m
it
s
Lim
D
N)
C
R
D
S
(O
10
0
4
4
10
-1
T
C
=25 C
Tj=150 C
Single Pulse
10
1
10
2
10
3
10
0
V
DS
, Drain-Source Voltage (V)
Figure 9. Gate Charge
Figure 10. Maximum Safe
Operating Area
V
DD
t
on
V
IN
D
V
GS
R
GEN
G
90%
t
off
t
r
90%
R
L
V
OUT
t
d(on)
V
OUT
t
d(off)
90%
10%
t
f
10%
INVERTED
S
V
IN
50%
10%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
r(t),Normalized Effective
Transient Thermal Impedance
10
0
D=0.5
0.2
10
-1
0.1
0.05
0.02
0.01
Single Pulse
P
DM
t
1
t
2
1. R
JC
(t)=r (t) * R
JC
2. R
JC
=See Datasheet
3. T
JM-
T
C
= P* R
JC
(t)
4. Duty Cycle, D=t1/t2
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
Square Wave Pulse Duration (sec)
Figure 13. Normalized Thermal Transient Impedance Curve
4-21
FPGA/CPLD
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