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IDT75K62413

产品描述Microcontroller
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小29KB,共1页
制造商IDT (Integrated Device Technology)
下载文档 详细参数 全文预览

IDT75K62413概述

Microcontroller

IDT75K62413规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
Reach Compliance Codeunknown
Base Number Matches1

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9M Network Search
Engine (NSE) with Quad
AMCC XSC Interface
Advanced
Information
IDT75K62413
To request the full datasheet, please contact your local
IDT Sales Representative or call 1-831-754-4555
Introduction
As part of the IDT IP Co-Processor product family, IDT delivers high
performance, feature-rich, easy-to-use, Network Search Engine (NSE)
products. Using CAM (Content Addressable Memory) technology, IDT
NSE products accelerate search functions for Access Control Lists (ACL),
Flow Caching, and forwarding to improve performance in next generation
networking equipment.
Device Description
The NSE Quad XSC interface is intended to work with any AMCC NPU
with an external search co-processor interface (XSC). It will operate with
multiple NPUs such as the nP3400 and nP7250, or can be used to satisfy
the four XSC requirements of the nP7510. The 75K62413 is compliant with
the XSC specification and the device may be optionally expanded up to
eight devices deep providing 2 million entries of 32-bit width.
Features
x
x
x
x
x
x
x
x
x
x
x
x
x
128K x 72 (9M) Data and Mask cells
Full Ternary Content Addressable Memory
Advanced Database Management
- Selectable Databases
- Programmable Width per Database
- Lookup widths from 32 to 512 bits
- Only the selected Database is powered
Maintenance Instructions
- Aging
- Multi Hit Invalidate
- Learn per Database
Support for Multiple Contexts
Pool of Global Mask Registers
Control and Management
- 32-bit Host control port featuring glueless PPC interface
- Capable of In-Band Control and Management
Associated Data SRAM is supported through a glueless ZBT®
interface
Lowest Power per Application
Synchronous Pipeline Operation
Boundary Scan JTAG Interface
1.2V Core Supply
3.3V I/O Supply for XSC I/O and ZBT® SRAM
Figure 1.0 AMCC NPU Interface
CPU
CPU Port
May be expanded up to 8 NSE devices
NPU#0
CPU
CPU
Request
Request
Optional
ASSOCIATED
ZBT SRAM
NPU#1
NPU#2
NPU#3
4 NPU
Request
Ports
NSE
#0
NSE
#1
NSE
#2
Result Interface
4 NPU
Response
Ports
One, two or four XSC interfaces can be enabled
6105 dw00
APRIL 2003
1
©
2002 Integrated Device Technology, Inc.
All rights reserved.
Product specifications subject to change without notice.
DSC-6105/00
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