HN29W25611T-50H
256M AND type Flash Memory
More than 16,057-sector (271,299,072-bit)
ADE-203-1178A (Z)
Rev. 1.0
May. 10, 2000
Description
The Hitachi HN29W25611T is a CMOS Flash Memory with AND type multi-level memory cells. It has fully
automatic programming and erase capabilities with a single 3.3 V power supply. The functions are controlled
by simple external commands. To fit the I/O card applications, the unit of programming and erase is as small
as (2048 + 64) bytes. Initial available sectors of HN29W25611T are more than 16,057 (98% of all sector
address) and less than 16,384 sectors.
Features
•
On-board single power supply (V
CC
): V
CC
= 3.3 V
±
0.3 V
•
Organization
AND Flash Memory: (2048 + 64) bytes
×
(More than 16,057 sectors)
Data register: (2048 + 64) bytes
•
Multi-level memory cell
2 bit/per memory cell
•
Automatic programming
Sector program time: 3.0 ms (typ)
System bus free
Address, data latch function
Internal automatic program verify function
Status data polling function
•
Automatic erase
Single sector erase time: 1.5 ms (typ)
System bus free
Internal automatic erase verify function
Status data polling function
HN29W25611T-50H
•
Erase mode
Single sector erase ((2048 + 64) byte unit)
•
Fast serial read access time:
First access time: 50
µs
(max)
Serial access time: 50 ns (max)
•
Low power dissipation:
I
CC2
= 50 mA (max) (Read)
I
SB2
= 50
µA
(max) (Standby)
I
CC3
/I
CC4
= 40 mA (max) (Erase/Program)
I
SB3
= 5
µA
(max) (Deep standby)
•
The following architecture is required for data reliability.
Error correction: more than 3-bit error correction per each sector read
Spare sectors: 1.8% (290 sectors) within usable sectors
Ordering Information
Type No.
HN29W25611T-50H
Available sector
More than 16,057 sectors
Package
12.0
×
18.40 mm
2
0.5 mm pitch
48-pin plastic TSOP I (TFP-48D)
2
HN29W25611T-50H
Memory Map and Address
Sector address
2048 bytes
3FFFH
3FFEH
3FFDH
2048 bytes
2048 bytes
64 bytes
64 bytes
64 bytes
2048 bytes
0002H
0001H
0000H
000H
2048 + 64 bytes
2048 bytes
2048 bytes
64 bytes
64 bytes
64 bytes
800H
83FH Column address
Control bytes
Address
Sector address
Cycles
SA (1):
SA (2):
Column address CA (1):
CA (2):
I/O0 I/O1 I/O2 I/O3
A0 A1 A2 A3
First cycle
Second cycle A8 A9 A10 A11
A0 A1 A2 A3
First cycle
Second cycle A8 A9 A10 A11
I/O4
A4
A12
A4
×
I/O5 I/O6 I/O7
A5 A6 A7
A13
×*
2
×
A5 A6 A7
×
×
×
Notes: 1. Some failed sectors may exist in the device. The failed sectors can be recognized
by reading the sector valid data written in a part of the column address 800 to 83F
(The specific address is TBD.). The sector valid data must be read and kept outside
of the sector before the sector erase. When the sector is programmed, the sector
valid data should be written back to the sector.
2. An
×
means "Don't care". The pin level can be set to either V
IL
or V
IH
, referred
to DC characteristics.
16057 - 16384 sectors *
1
5
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