HD74HC393
Dual 4-bit Binary Counters
REJ03D0625-0200
(Previous ADE-205-504)
Rev.2.00
Mar 30, 2006
Description
The HD74HC393 contain two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-256
counter.
The HD74HC393 is incremented on the high to low transition (negative edge) of the clock input, and each has an
independent clear input. When clear is set high all four bits of each counter are set to a low level. This enables count
truncation and allows the implementation of divide-by-N counter configurations.
Features
•
High Speed Operation: t
pd
(A to Q
A
) = 16 ns typ (C
L
= 50 pF)
•
High Output Current: Fanout of 10 LSTTL Loads
•
Wide Operating Voltage: V
CC
= 2 to 6 V
•
Low Input Current: 1
µA
max
•
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max (Ta = 25°C)
•
Ordering Information
Part Name
HD74HC393P
HD74HC393FPEL
Package Type
DILP-14 pin
SOP-14 pin (JEITA)
Package Code
(Previous Code)
PRDP0014AB-B
(DP-14AV)
PRSP0014DF-B
(FP-14DAV)
P
FP
Package
Abbreviation
—
EL (2,000 pcs/reel)
Taping Abbreviation
(Quantity)
Note: Please consult the sales office for the above package availability.
Function Table
Clock
X
H
L
Clear
H
L
L
L
L
Note:
1. H; High level, L; Low level, X; Irrelevant
Outputs
L
No change
No change
No change
Advance to next state
Rev.2.00 Mar 30, 2006 page 1 of 6
HD74HC393
Pin Arrangement
1A
1Clear
1Q
A
1Q
B
1Q
C
1Q
D
GND
1
2
3
4
5
6
7
CLR
Q
A
Q
B
A
A
Q
C
Q
D
Q
C
Q
D
CLR
Q
A
Q
B
14
13
12
11
10
9
8
V
CC
2A
2Clear
2Q
A
2Q
B
2Q
C
2Q
D
Outputs
(Top view)
Logic Diagram
Clock
C
D
Q
Q
Q
A
Outputs
C
D
Q
Q
Q
B
C
D
Q
Q
Q
C
C
D
Clear
Q
Q
Q
D
Rev.2.00 Mar 30, 2006 page 2 of 6
HD74HC393
Absolute Maximum Ratings
Item
Supply voltage range
Input / Output voltage
Input / Output diode current
Output current
V
CC
, GND current
Power dissipation
Symbol
V
CC
V
IN
, V
OUT
I
IK
, I
OK
I
OUT
I
CC
or I
GND
P
T
Ratings
–0.5 to 7.0
–0.5 to V
CC
+0.5
±20
±25
±50
500
Unit
V
V
mA
mA
mA
mW
Storage temperature
Tstg
–65 to +150
°C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item
Supply voltage
Input / Output voltage
Operating temperature
Input rise / fall time
Note:
*1
Symbol
V
CC
V
IN
, V
OUT
Ta
t
r
, t
f
Ratings
2 to 6
0 to V
CC
–40 to 85
0 to 1000
0 to 500
Unit
V
V
°C
ns
Conditions
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
0 to 400
1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Item
Input voltage
Symbol V
CC
(V)
V
IH
2.0
4.5
6.0
2.0
4.5
6.0
Output voltage
V
OH
2.0
4.5
6.0
4.5
V
OL
6.0
2.0
4.5
6.0
4.5
6.0
Input current
Quiescent supply
current
Iin
I
CC
6.0
6.0
Ta = 25°C
Min
Typ Max
1.5
3.15
4.2
—
—
—
1.9
4.4
5.9
4.18
5.68
—
—
—
—
—
—
—
—
—
—
—
—
—
2.0
4.5
6.0
—
—
0.0
0.0
0.0
—
—
—
—
—
—
—
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
Ta = –40 to+85°C
Unit
Min
Max
1.5
3.15
4.2
—
—
—
1.9
4.4
5.9
4.13
5.63
—
—
—
—
—
—
—
—
—
—
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.33
0.33
±1.0
40
I
OH
= 4 mA
I
OH
= 5.2 mA
µA
Vin = V
CC
or GND
µA
Vin = V
CC
or GND, Iout = 0
µA
V
Vin = V
IH
or V
IL
V
Vin = V
IH
or V
IL
I
OH
= –20
µA
V
Test Conditions
V
IL
V
I
OH
= –4 mA
I
OH
= –5.2 mA
I
OL
= 20
µA
Rev.2.00 Mar 30, 2006 page 3 of 6
HD74HC393
Switching Characteristics
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Ta = 25°C
Item
Maximum clock
frequency
Propagation delay
time
Symbol V
CC
(V)
f
max
2.0
4.5
6.0
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Removal time
t
h
2.0
4.5
6.0
2.0
4.5
6.0
—
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
80
16
14
50
10
9
—
—
—
—
Typ
—
—
—
—
16
—
—
20
—
—
24
—
—
28
—
—
21
—
—
—
—
—
—
—
—
5
—
5
Max
5
25
29
120
24
20
185
37
31
220
44
37
260
52
44
150
30
28
—
—
—
—
—
—
75
15
13
10
Ta = –40 to +85°C
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
20
17
65
13
11
—
—
—
—
Max
4
20
24
150
30
26
230
46
39
275
55
47
325
65
55
190
38
33
—
—
—
—
—
—
95
19
16
10
pF
ns
Clear to clock
ns
Clear to Q
A
, Q
B
, Q
C
, Q
D
ns
Clock to Q
C
ns
Clock to Q
A
Unit
MHz
Test Conditions
ns
Clock to Q
B
ns
Clock to Q
D
Pulse width
t
w
ns
Clock, clear
Output rise/fall
time
Input capacitance
t
TLH
t
THL
Cin
ns
Test Circuit
V
CC
V
CC
Output
Q
A
See Function Table
Input
Pulse Generator
Z
out
= 50
Ω
Input
Pulse Generator
Z
out
= 50
Ω
A
Q
B
Q
C
Clear
Q
D
Output
Output
Output
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
Note : 1. C
L
includes probe and jig capacitance.
Rev.2.00 Mar 30, 2006 page 4 of 6
HD74HC393
Waveforms
•
Waveform – 1
t
r
t
f
V
CC
Clock
50%
50%
50%
50%
t
w
t
w
t
PHL (Measure at tn+2)
90%
50%
10%
0V
t
PLH (Measure at tn+1)
90%
50%
10%
V
OH
V
OL
V
OH
V
OL
Q
A
t
THL
t
PHL (Measure at tn+4)
90%
50%
10%
t
TLH
t
PLH (Measure at tn+2)
90%
50%
10%
Q
B
t
THL
t
PHL (Measure at tn+8)
90%
t
TLH
t
PLH (Measure at tn+4)
90%
50%
10%
V
OH
V
OL
Q
C
50%
10%
t
THL
t
TLH
t
PHL (Measure at tn+16)
t
PLH (Measure at tn+8)
90%
90%
50%
10%
50%
10%
V
OH
V
OL
Q
D
t
THL
t
TLH
Notes: 1. Input waveform: PRR
≤
1 MHz, Zo = 50
Ω,
t
r
≤
6 ns, t
f
≤
6 ns
2. tn is bit time with all outputs at low.
•
Waveform – 2
t
r
90 %
50 % 50 %
10 %
t
w(clear)
t
PHL
90%
t
f
V
CC
10 %
0V
Clear
V
OH
50 %
10%
Q
A
to Q
D
V
OL
t
THL
Notes: 1. Input waveform: PRR
≤
1 MHz, Zo = 50
Ω,
t
r
≤
6 ns, t
f
≤
6 ns
2. The output are measured one at a time with one transition per measurement.
Rev.2.00 Mar 30, 2006 page 5 of 6
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