®
M34116
PCM CONFERENCE CALL
AND TONE GENERATION CIRCUIT
HW AND SW COMPATIBLE WITH M116
1 TO 64 SERIAL CHANNELS PER FRAME
(CONTROLLED BY SYNC SIGNAL PERIOD)
29 MAXIMUM CONFERENCES
1 TO 64 SERIAL CHANNELS PER CONFER-
ENCES
3 SIMULTANEOUS OPERATION MODES
AVAILABLE:
CONFERENCE, TRANSPARENT AND TONE
GENERATION
TYPICAL BIT RATES:
1536/1544/2048/4096 Kbits/s
COMPATIBLE WITH ALL KINDS OF PCM
FORMAT
µ
AND A LAW (PIN PROGRAMMABLE)
EQUAL PRIORITY TO EVERY CHANNEL
ONE FRAME AND ONE CHANNEL DELAY
FROM SENDING TO RECEIVING
OVERFLOW INFORMATION FOR EACH CON-
FERENCE BY PIN OS (OVERFLOW SIGNAL-
LING) AND ON DATA BUS ON MPU RE-
QUEST
INSTRUCTION SET COMPATIBLE WITH M3488
PROGRAMMABLE INPUT AND OUTPUT AT-
TENUATION OR GAIN FROM 0 TO 15dB
WITH STEP OF 1dB FOR EACH CHANNEL
TONE GENERATION FROM 3.9Hz TO
3938Hz WITH MIN. STEP OF 3.9Hz
TOTAL OF 7 DIFFERENT TONE OUTPUTS
IN PARALLEL PROGRAMMABLE VIA MPU
(MAXIMUM 4 DIFFERENT FREQUENCIES
AND DURATIONS)
1 MELODY OF MAXIMUM 32 PROGRAMMA-
BLE FREQUENCIES AND DURATIONS
5V POWER SUPPLY
TTL
COMPATIBLE
INPUT
LEVELS,
CMOS/TTL COMPATIBLE OUTPUT LEVELS
MAIN INSTRUCTIONS CONTROLLED BY MI-
CROPROCESSOR INTERFACE:
– Channel connection to a conference
– Channel attenuation or gain
– Channel disconnection from both conference
and transparent modes
– Tone and melody generation
– Overflow status
– Operating mode
– Channel status
September 2003
DIP24
ORDERING NUMBER:
M34116B1
PLCC28
ORDERING NUMBER:
M34116C1
DESCRIPTION
The M34116 is a product specifically designed for
applications in PCM digital exchanges. It is able
to handle up to 64 channels in any conferences
combination from 1 to 29 conferences in parallel
and to generate seven different tones and one
melody.
The parties in a conference must previously be al-
located through the Digital Switching Matrix
(M3488) in a single serial wire at M34116 PCM
input (IN PCM pin).
The M34116 is full pin and function compatible
with the M116. In addition, it has the capability to
generate tone directly coded in PCM.
For the conference function, each channel is con-
verted inside the chip from PCM law to linear law
(14 bits). Then it is added to its conference, and
the sample of the previous frame is subtracted
from the conference.
In this way a new conference sum signal is gener-
ated.
The channel output signal will contain the infor-
mation of all the other channels in its conference
except its own.
After the PCM encoding, the data is serialized by
the M34116 in the same sequence as the PCM
input frame, with one frame (plus one channel)
delay and will be reallocated by the DSM (M3488)
at the final channel and bus position.
A programmable attenuation or gain can be set
on each channel and for every function: confer-
ence, tone generation and transparent mode.
1/23
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M34116
PIN CONNECTIONS
(Top view)
DIP24
PLCC28
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
(*)
V
i
V
O (off)
P
tot
T
stg
T
op
Supply Voltage
Input Voltage
Off State Output Voltage
Total Power Dissipation
Storage Temperature
Operating Temperature
Parameter
Value
– 0.3 to 7
– 0.3 to V
DD
– 0.3 to 7
500
– 65 to 150
0 to 70
V
mW
°C
°C
Unit
V
Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1:
PCM Conference Call Insertion Scheme
2/23
M34116
PIN DESCRIPTION
DIP
N
o
1
PLCC
N
o
2
Pin
TD
Function
2
3
4
5
6 to 13
14
15
16
17
18
19
20
21
22
23
24
M116 operating mode only. Tone Duration input pin. When TD = 1, a PCM coded tone
(instead of PCM data) is sent out to all channels enabled by the IT bit. TD is latched by
the SYNC signal so that all channels have the same tone during the same number of
frames. TD = 0 for normal operation.
3
TF
M116 operating mode only. Tone Frequency input pin. When TF = 1, the tone amplitude
is high. When TF = 0, the tone amplitude is low. TF is latched by SYNC. The PCM coded
tone level corresponds to 1/10 of the full scale. For M34116 operating mode: Melody
waveform select input pin. When TF = 1, the PCM output of the melody represents a
square wave. When TF = 0, it represents a sine wave. In both cases, the rms level is the
same and is equal to – 6 dBm0 if no attenuation or gain is programmed.
RESET Master reset input pin. This pin is active low and must be used at the very beginning after
4
power up to initialize the device or when switching from A law to Mu law. The Internal
initialization routine takes 2 time frames starting from the rising edge of RESET. During
this initialization time, all data bus and PCM output are pulled to a high impedance state.
OS
Overflow Signalling output pin. When OS = 0 one conference is in overflow. This signal is
5
anticipated over half time slot with respect to the output channel involved in the conference in
overflow. Example: if output channel 4 is one of the parties of one conference in
overflow, OS = 0 during the second half of the time slot corresponding to output channel 3
and during the first half of the time slot corresponding to output channel 4.
6
OUT PCM output pin. The bit rate is 4096Kbits/s max. The sign bit is the first bit of the serial
PCM sequence. The first bit of the first channel is found at the rising edge of the CLOCK signal
preceding the rising edge of the SYNC signal. The output buffer is open drain to allow for
multiple connections.
7,
D0 to Bidirectional Data bus pins. Data and instructions are transferred to or from the
9 to 11,
D7
microprocessor. D0 is the Least Significant Bit. The bus is tristate when RESET is low
and/or CS is high.
13 to 16
17
VDD +5V Supply input. 100nF decoupling capacitor recommended.
Control Data input pin. In a write operation C/D = 0 qualifies any bus content as data
18
C/D
while C/D = 1 qualifies it as an opcode. For M116 operating mode only: in a read
operation, the overflow information of the first eight conferences is selected by C/D = 0,
the overflow of the last two conferences and the status by C/D = 1.
CS
Chip Select input pin. When CS = 0, data and instructions can be transferred to or from
19
the external microprocessor and when CS = 1 the data bus is in tristate.
RD
Read control input pin. When RD = 0, read operation is performed. When match
20
conditions for the opcode exists, data is transferred to the external microprocessor on the
falling edge of RD.
WR
Write control input pin. Instructions and opcode from the external microprocessor are
21
latched on the rising edge of WR.
SYNC Synchronization input pin. The rising edge of CLOCK preceding the rising edge of SYNC
23
corresponds to the first bit of the first channel except for PCM frame of 1544Kbits/s. In
this case, it corresponds to the Extra bit (193th).
24
CLOCK Master Clock input pin. Typ. operating Frequencies are:
3.072MHz for 24 PCM channels frame (192 bit/frame)
3.088MHz for 24 PCM channels frame with extra bit (193 bit/frame)
4.096MHz for 32 PCM channels frame (256 bit/frame)
8.192MHz for 64 PCM channels frame (512 bit/frame)
Both M34116 an M116 operating modes are possible up to 4.096MHz.
At 8.192MHz only M34116 operating mode is possible.
25
EC
External Clock output pin. This pin provides the master clock for the Digital Switching
Matrix (M3488). Normally it is the same signal as applied to the CLOCK input (pin 20).
When the Extra bit is selected with the instruction 5, the first two periods of the master
clock are canceled in order to allow the operation of the M34116 and the DSM with PCM
frame with Extra bit (e.g. 193 bit/frame with PCM I/O of 1544Kbits/s).
27
IN PCM PCM input pin. The max bit rate is 4096Kbits/s. The first bit of the first cahnnel is found at
the second rising edge of the CLOCK signal following the rising edge of the SYNC signal.
If Extra bit is selected, then the first bit is shifted by two CLOCK periods.
A Law or MU Law select pin. When A/MU = 1, A Law is selected. When A/MU = 0, MU Law is
28
A/MU
selected. The law selection must be done before initializing the device using the RESET pin.
1
Vss
Ground.
3/23
M34116
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
i
V
O
CLOCK Freq.
SYNC Freq.
T
op
Supply Voltage
Input Voltage
Off State Output Voltage
Input Clock Frequency
Input Synchronization Frequency
Operating Temperature
Parameter
Value
4.75 to 5.25
0 to 5.25
0 to 5.25
3.072/3.088
4.096 / 8.192 (*)
8
0 to 70
Unit
V
V
V
MHz
MHz
KHz
°C
CAPACITANCES
(measurements frequency = 1MHz; 0 to 70°C; unused pins tied to V
SS
)
Symbol
C
I
C
I/O
C
O
Parameter
Input Capacitance
I/O Capacitance
Output Capacitance
6 to 13
4, 5, 21
Pin (**)
1 to 3; 15 to 20; 22 to 23
Min.
Typ.
Max.
5
15
10
Unit
pF
pF
pF
ELECTRICAL CHARACTERISTICS
(Tamb = 0 to 70°C, V
CC
= 5V
±
5%)
All DC characteristic are valid 250µs after V
CC
and clock have been applied.
Symbol
V
IL
Parameter
Input Low Level
Pins (**)
1 to 3
15 to 20
22 to 23
1 to 3
15 to 20
22 to 23
6 to 13 (***)
6 to 13 (***)
6 to 13 (***)
4,6 to 13,21
4 to 13, 21
5
1 to 3
6 to 13
15 to 20
22 to 23
6 to 13
14
V
CC
= 5V
V
CC
= 5V
V
CC
= 5V
I
OL
= 2mA
I
OH
= 1mA
I
OL
= 4.1mA
V
IN
= 0 to V
CC
V
CC
-0.4
0.4
10
Test Condition
Min.
– 0.3
Typ.
Max.
+0.8
Unit
V
V
IH
Input High Level
2.0
V
CC
V
V
T–
V
T+
V
HY
V
OL
V
OH
V
OL
I
IL
Negative Threshold
Voltage
Positive Threshold
Voltage
Hysteresis
Output Low Level
Output High Level
Output Low Level
Input Leakage Current
0.6
1.5
0.4
0.9
1.7
0.8
1.1
2
V
V
V
0.4
V
V
V
µA
I
OL
I
CC
Data Bus Leakage
Current
Supply Current
V
IN
= 0 to V
CC
CS = V
CC
Clock Freq. = 4.096MHz
±10
50
µA
mA
(*) Only in M34116 Operating Mode.
(**) Pin numbers referred to the DIP24.
(***) Schimitt-trigger inputs.
4/23
M34116
ELECTRICAL CHARACTERISTICS
(Tamb = 0 to 70°C, V
CC
= 5V
±
5%)
All DC characteristic are valid 250µs after V
CC
and clock have been applied. C
L
is the max. capacitive
load and R
L
the test pull up resistor.
Signal
CK
Up to
4.096MHz
Symbol
t
CK
t
WL
t
WH
t
R
t
F
t
CK
t
WL
t
WH
t
R
t
F
t
SL
t
HL
t
SH
t
WH
t
S
t
H
t
PD min.
t
PD max.
t
SL
t
HL
t
SH
t
WH
t
WL
t
WH
t
REP
t
SH
t
HH
t
R
t
F
RD
t
WL
t
WH
t
REP
t
SH
t
HH
t
R
t
F
Notes:
1. With Extra Bit operating mode insert this time becomes 3 t
CK
.
2. With Extra Bit operating mode insert these times are 80ns longer.
3. With OPCODE (C/D = I), this time becomes 4tck (6tck if E = 1). E: extra bit indication in "operating mode" instruction.
4. For tone generation instruction, this time becomes 4tck (6tck if E = 1) E: extra bit indication in "operating mode" instruction.
5. With extra bit operating mode insert, this time becomes 6tck.
6. The initialization routine takes 2 frames time starting from the rising edge of RESET - Any access to the device should take place after the
initialization routine is completed. (2 frames time).
Parameter
Clock Period
Clock Low Level Width
Clock High Level Width
Rise Time
Fall Time
Clock Period
Clock Low Level Width
Clock High Level Width
Rise Time
Fall Time
Low Level Set-up Time
Low Level Hold Time
High Level Set-up Time
High Level Width
Set-up Time
Hold Time
Propagation Time Low
Level referred to CK
Propagation Time High
level Referred to CK
Low Level Set-up Time
Low Level Hold Time
High Level Set-up Time
High Level Width
Low Level Width
High Level Width
Repetition interval
between active pulses.
High Level st-up time to
active read strobe.
High Level hold time to
active read strobe.
Rise Time
Fall Time
Low Level Width
High Level Width
Repetition interval
between active pulses.
High Level st-up time to
active read strobe.
High Level hold time to
active read strobe.
Rise Time
Fall Time
Test Condition
Min.
230
100
100
Typ.
Max.
25
25
120
50
50
10
10
See note 1
30
30
30
t
CK
35
35
C
L
= 50pF R
L
= 1KΩ
40
180
note 6
50
30
30
t
CK
150
200
500
0
20
60
60
180
200
4 t
CK
0
20
60
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
8.192MHz
SYNC
PCM In-
put
PCM
Output
(Open
drain)
RESET
WR
note 3 and 4
note 5
5/23
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
