MITSUBISHI MICROCOMPUTERS
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 4501 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a
simple, high-speed instruction set. The computer is equipped with
two 8-bit timers (each timer has a reload register), interrupts, and
10-bit A-D converter.
The various microcomputers in the 4501 Group include variations
of the built-in memory size as shown in the table below.
FEATURES
qMinimum
instruction execution time ................................ 0.68
µ
s
(at 4.4 MHz oscillation frequency, in high-speed mode)
qSupply
voltage ......................................................... VRST to 5.5 V
(VRST: detection voltage of voltage drop detection circuit)
qTimers
Timer 1 ...................................... 8-bit timer with a reload register
Timer 2 ...................................... 8-bit timer with a reload register
qInterrupt
........................................................................ 4 sources
qKey-on
wakeup function pins ................................................... 12
qInput/Output
port ...................................................................... 14
qA-D
converter .................. 10-bit successive comparison method
qWatchdog
timer
qClock
generating circuit (ceramic resonator/RC oscillation)
qLED
drive directly enabled (port D)
qPower-on
reset circuit
qVoltage
drop detection circuit ........................... VRST: Typ. 3.5 V
(Ta = 25 °C)
APPLICATION
Electrical household appliance, consumer electronic products, of-
fice automation equipment, etc.
ROM (PROM) size
(✕ 10 bits)
2048 words
4096 words
4096 words
RAM size
(✕ 4 bits)
128 words
256 words
256 words
Product
M34501M2-XXXFP
M34501M4-XXXFP
M34501E4FP (Note)
Package
20P2N-A
20P2N-A
20P2N-A
ROM type
Mask ROM
Mask ROM
One Time PROM
Note:
Shipped in blank.
PIN CONFIGURATION
V
DD
V
SS
X
IN
X
OUT
CNV
SS
RESET
P2
1
/A
IN1
P2
0
/A
IN0
D
3
/K
D
2
/C
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
P0
0
P0
1
P0
2
P0
3
P1
0
P1
1
P1
2
/CNTR
P1
3
/INT
D
0
D
1
Outline 20P2N-A
Pin configuration (top view) (4501 Group)
M34501Mx-XXXFP
M34501E4FP
Block diagram (4501 Group)
2
4
4
2
4
BLOCK DIAGRAM
I/O port
Port P1
Port P2
Port D
Port P0
Internal peripheral functions
System clock generating circuit
X
IN
-X
OUT
Power-on reset circuit
Voltage drop detection circuit
Timer
Timer 1 (8 bits)
Timer 2 (8 bits)
Watchdog timer
(16 bits)
Memory
ROM
2048, 4096 words
✕
10 bits
A-D converter
(10 bits
✕
2 ch)
4500 Series
CPU core
ALU (4 bits)
Register A (4 bits)
Register B (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack register SK (8 levels)
Interrupt stack register SDP (1level)
RAM
128, 256 words
✕
4 bits
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
4501 Group
MITSUBISHI MICROCOMPUTERS
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PERFORMANCE OVERVIEW
Parameter
Number of basic instructions
Minimum instruction execution time
Memory sizes ROM
M34501M2
M34501M4/E4
RAM
M34501M2
M34501M4/E4
Input/Output D
0
–D
3
I/O
ports
Function
111
0.68
µ
s (at 4.4 MHz oscillation frequency, in high-speed mode)
2048 words
✕
10 bits
4096 words
✕
10 bits
128 words
✕
4 bits
256 words
✕
4 bits
Four independent I/O ports.
Input is examined by skip decision.
Ports D
2
and D
3
are equipped with a pull-up function and a key-on wakeup function. Both func-
tions can be switched by software.
Ports D
2
and D
3
are also used as ports C and K, respectively.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
Ports P1
2
and P1
3
are also used as CNTR and INT, respectively.
2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
Ports P2
0
and P2
1
are also used as A
IN0
and A
IN1
, respectively.
1-bit I/O; Port C is also used as port D
2
.
1-bit I/O; Port K is also used as port D
3
.
1-bit I/O; CNTR pin is also used as port P1
2
.
1-bit input; INT pin is also used as port P1
3
.
Two independent I/O ports. A
IN0
–A
IN1
is also used as ports P2
0
, P2
1
, respectively.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register and has a event counter.
10-bit wide, This is equipped with an 8-bit comparator function.
2 channel (A
IN0
pin, A
IN1
pin)
4 (one for external, two for timer, one for A-D)
1 level
8 levels
CMOS silicon gate
20-pin plastic molded SOP (20P2N-A)
–20 °C to 85 °C
VRST to 5.5 V (VRST: detected voltage of voltage drop detection circuit. Refer to the voltage
drop detection circuit characteristics.)
1.7 mA (at V
DD
= 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors
in the cut-off state)
0.1
µ
A (at room temperature, V
DD
= 5 V, output transistors in the cut-off state)
P0
0
–P0
3
I/O
P1
0
–P1
3
I/O
P2
0
, P2
1
I/O
C
K
CNTR
INT
A
IN0
, A
IN1
Timers
A-D converter
Timer 1
Timer 2
I/O
I/O
Timer I/O
Interrupt input
Analog input
Analog input
Interrupt
Sources
Nesting
Subroutine nesting
Device structure
Package
Operating temperature range
Supply voltage
Power
Active mode
dissipation
(typical value) RAM back-up mode
3
MITSUBISHI MICROCOMPUTERS
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
V
DD
V
SS
CNV
SS
RESET
Name
Power supply
Ground
CNV
SS
Reset input/output
Function
Input/Output
Connected to a plus power supply.
—
Connected to a 0 V power supply.
—
Connect CNV
SS
to V
SS
and apply “L” (0V) to CNV
SS
certainly.
—
I/O
An N-channel open-drain I/O pin for a system reset. When the watchdog timer or the
voltage drop detection circuit cause the system to be reset, the RESET pin outputs
“L” level.
I/O pins of the system clock generating circuit. When using a ceramic resonator, connect
it between pins X
IN
and X
OUT
. A feedback resistor is built-in between them. When using
the RC oscillation, connect a resistor and a capacitor to X
IN
, and leave X
OUT
pin open.
Each pin of port D has an independent 1-bit wide I/O function. Each pin has an out-
put latch. For input use, set the latch of the specified bit to “1.” Input is examined by
skip decision. The output structure is N-channel open-drain. Ports D
2
and D
3
are
equipped with a pull-up function and a key-on wakeup function. Both functions can
be switched by software.
Ports D
2
and D
3
are also used as ports C and K, respectively.
Port P0 serves as a 4-bit I/O port, and it can be used as inputs when the output latch
is set to “1.” The output structure is N-channel open-drain. Port P0 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Port P1 serves as a 4-bit I/O port, and it can be used as inputs when the output latch
is set to “1.” The output structure is N-channel open-drain. Port P1 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P1
2
and P1
3
are also used as CNTR and INT, respectively.
Port P2 serves as a 2-bit I/O port, and it can be used as inputs when the output latch
is set to “1.” The output structure is N-channel open-drain. Port P2 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P2
0
and P2
1
are also used as A
IN0
and A
IN1
, respectively.
1-bit I/O port. Port C can be used as inputs when the output latch is set to “1.” The
output structure is N-channel open-drain. Port C has a key-on wakeup function and
a pull-up function. Both functions can be switched by software. Port C is also used
as port D
2
.
1-bit I/O port. Port K can be used as inputs when the output latch is set to “1.” The
output structure is N-channel open-drain. Port K has a key-on wakeup function and
a pull-up function. Both functions can be switched by software. Port K is also used
as port D
3
.
CNTR pin has the function to input the clock for the timer 2 event counter, and to out-
put the timer 1 or timer 2 underflow signal divided by 2. This pin is also used as port
P1
2
.
INT pin accepts external interrupts. It has the key-on wakeup function which can be
switched by software. This pin is also used as port P1
3
.
A-D converter analog input pins. A
IN0
and A
IN1
are also used as ports P2
0
and P2
1
,
respectively.
X
IN
X
OUT
D
0
–D
3
System clock input
System clock output
I/O port D
Input
Output
I/O
P0
0
–P0
3
I/O
I/O
P1
0
–P1
3
I/O port P1
I/O
P2
0
, P2
1
I/O port P2
I/O
Port C
I/O port C
I/O
Port K
I/O port K
I/O
CNTR
Timer input/output
I/O
INT
A
IN0
–A
IN1
Interrupt input
Analog input
Input
Input
MULTIFUNCTION
Pin
D
2
D
3
P1
2
P1
3
Multifunction
C
K
CNTR
INT
C
K
CNTR
INT
Pin
D
2
D
3
P1
2
P1
3
Multifunction
Pin
P2
0
P2
1
Multifunction
A
IN0
A
IN1
Pin
A
IN0
A
IN1
Multifunction
P2
0
P2
1
Notes 1: Pins except above have just single function.
2: The input/output of D
2
, D
3
, P1
2
and P1
3
can be used even when C, K, INT and CNTR (input) are selected.
3: The input of P1
2
can be used even when CNTR (output) is selected.
4: The input/output of P2
0
, P2
1
can be used even when A
IN0
, A
IN1
are selected.
4
MITSUBISHI MICROCOMPUTERS
4501 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DEFINITION OF CLOCK AND CYCLE
q
Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• External ceramic resonator
• External RC oscillation
• Clock (f(X
IN
)) by the external clock
• Clock (f(RING)) of the ring oscillator which is the internal oscil-
lator.
q
System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the bits 2 and 3 of the clock con-
trol register MR.
Table Selection of system clock
Register MR
System clock
MR
3
MR
2
(Note 1)
0
0
f(X
IN
) or f(RING)
0
1
f(X
IN
)/2 or f(RING)/2
1
0
f(XIN)/4 or f(RING)/4
1
1
f(XIN)/8 or f(RING)/8
q
Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.
q
Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Operation mode
High-speed mode
Middle-speed mode
Low-speed mode
Default mode
Notes 1:
The ring oscillator clock is f(RING), the clock by the ce-
ramic resonator, RC oscillation or external clock is f(X
IN
).
2:
The default mode is selected after system is released
from reset and is returned from RAM back-up.
PORT FUNCTION
Port
Port D
D
0
, D
1
D
2
/C
D
3
/K
Pin
Input
Output
I/O
(4)
Output structure
N-channel open-drain
I/O
unit
1
Control
instructions
SD, RD
SZD, CLD
SCP, RCP
SNZCP
IAK, OKA
OP0A
IAP0
Control
registers
PU2, K2
Remark
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Port P0 P0
0
–P0
3
I/O
(4)
N-channel open-drain
4
PU0, K0
Port P1 P1
0
, P1
1
P1
2
/CNTR,
P1
3
/INT
Port P2 P2
0
/A
IN0
P2
1
/A
IN1
I/O
(4)
N-channel open-drain
4
OP1A
IAP1
PU1, K1
W6, I1
I/O
(2)
N-channel open-drain
2
OP2A
IAP2
PU2, K2
Q1
5
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