M34A02
2 Kbit Serial SMBus EEPROM for ACR Card Configuration
PRODUCT PREVIEW
s
s
s
s
s
s
s
s
s
s
Two Wire SMBus Serial Interface
2.7V to 3.6V Single Supply Voltage
Hardware Write Control
BYTE and PAGE WRITE (up to 16 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Behavior
More than 1 Million Erase/Write Cycles
More than 40 Year Data Retention
8
1
SO8 (MN)
150 mil width
DESCRIPTION
These electrically erasable programmable
memory (EEPROM) devices are organized as
256x8 bits, and operate down to 2.7 V.
These devices are available in Plastic Small
Outline and Thin Shrink Small Outline packages.
These devices are written by the ACR card-issuer,
and then accessed in Read mode in the
application, using the ACR Serial Bus protocol.
This is a two wire serial interface that uses a bi-
directional data bus and serial clock. The device
carries a built-in 4-bit Device Type Identifier code
(1011).
The device behaves as a slave in the ACR Serial
Bus protocol, with all memory operations
synchronized by the serial clock. Read and Write
operations are initiated by a Start condition,
generated by the bus master. The Start condition
8
1
TSSOP8 (DW)
169 mil width
Figure 1. Logic Diagram
VCC
3
E0-E2
SDA
M34A02
Table 1. Signal Names
E0, E1, E2
SDA
SCL
WC
V
CC
V
SS
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
SCL
WC
VSS
AI03794
April 2001
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/15
M34A02
Figure 2. SO and TSSOP Connections
Figure 3. Typical ACR Application PCB
Connection (showing E2,E1,E0 address 000)
VCC
M34A02
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
AI03795
E0
VCC
WC
SCL
SDA
E1
E2
VSS
VSS
VCC
WC
SCL
SDA
RL
ACR Bus
AI04092
Note: 1. This arrangement on the chip enable lines allows the
application to start at ACR address 000h.
is followed by a Device Select code and RW bit (as
described in Table 3), terminated by an
acknowledge bit.
When writing data to the memory, the device
inserts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
CC
has reached the POR
Table 2. Absolute Maximum Ratings
1
Symbol
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature during
Soldering
Input or Output range
Supply Voltage
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V
CC
drops from the operating
voltage, below the POR threshold value, all
operations are disabled and the device will not
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this line is
used by slave devices to synchronize the bus to a
slower clock, the bus master must have an open
drain output, and a pull-up resistor must be
connected from Serial Clock (SCL) to V
CC
. (Figure
3 indicates how the value of the pull-up resistor
Value
–40 to 125
–65 to 150
Unit
°C
°C
°C
V
V
V
SO8: 20 seconds (max)
2
TSSOP8: 20 seconds (max)
2
235
235
–0.6 to 6.5
–0.3 to 6.5
4000
Electrostatic Discharge Voltage (Human Body model)
3
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality
documents.
2. IPC/JEDEC J-STD-020A
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500
Ω,
R2=500
Ω)
2/15
M34A02
can be calculated). In most applications, though,
this method of synchronization is not employed,
and so the pull-up resistor is not necessary,
provided that the bus master has a push-pull
(rather than open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V
CC
.
(Figure 3 indicates how the value of the pull-up
resistor can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. These
inputs should be tied to V
CC
or V
SS
, to establish
the Device Select Code.
Write Control (WC)
This input signal is useful for protecting the entire
contents of the memory from inadvertent erase
and write operations. Write operations are
disabled to the entire memory array when Write
Control (WC) is held High. When unconnected, the
signal is internally read as V
IL
, and Write
operations are allowed.
When Write Control (WC) is held High, Device
Select and Address bytes are acknowledged,
Data bytes are
not
acknowledged.
DEVICE OPERATION
The device supports the ACR Serial Bus protocol.
This is summarized in Figure 4. Any device that
sends data on to the bus is defined to be a
transmitter, and any device that reads the data to
be a receiver. The device that controls the data
transfer is known as the bus master, and the other
as the slave device. A data transfer can only be
initiated by the bus master, which will also provide
the serial clock for synchronization. The device is
always a slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of the SDA line
while the clock SCL is stable in the High state. A
Stop
condition
terminates
communication
between the device and the bus master. A Stop
condition at the end of a Read command, provided
that it is followed by NoAck, forces the device into
its Stand-by mode. A Stop condition at the end of
a Write command triggers the internal EEPROM
Write cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a
successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases
Serial Data (SDA) after sending eight bits of data.
During the 9
th
clock pulse period, the receiver pulls
Serial Data (SDA) Low to acknowledge the receipt
of the eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
Figure 4. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an ACR Serial Bus
VCC
20
Maximum RP value (kΩ)
16
RL
12
8
4
0
10
100
CBUS (pF)
AI01665
RL
SDA
MASTER
fc = 100kHz
fc = 400kHz
SCL
CBUS
CBUS
1000
3/15
M34A02
Figure 5. ACR Serial Bus Protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START
Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP
Condition
AI00792B
For correct device operation, Serial Data (SDA)
must be stable before the rising edge of Serial
Clock (SCL), and the data must change
only
after
Serial Clock (SCL) is Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the 8-bit byte, shown in Table 3, on Serial
Data (SDA) (most significant bit first). This
consists of the 7-bit Device Select code, and the
Read/Write bit (RW).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1011b.
Up to eight memory devices can be connected on
a single bus. Each one is given a unique 3-bit code
on Chip Enable (E0, E1, E2). When the Device
Select Code is received on Serial Data (SDA), the
device only responds if the Chip Select Code is the
Table 3. Device Select Code
1
Device Type Identifier
b7
Device Select Code
1
b6
0
b5
1
b4
1
b3
E2
Chip Enable
b2
E1
b1
E0
RW
b0
RW
Note: 1. The most significant bit, b7, is sent first.
4/15
M34A02
Table 4. Operating Modes
Mode
Current Address Read
Random Address Read
1
Sequential Read
Byte Write
Page Write
Note: 1. X =
V
IH
or V
IL
.
RW bit
1
0
WC
1
X
X
Bytes
1
1
Initial Sequence
START, Device Select, RW = 1
START, Device Select, RW = 0, Address
reSTART, Device Select, RW = 1
X
X
V
IL
V
IL
≥
1
1
1
0
0
Similar to Current or Random Address Read
START, Device Select, RW = 0
≤
16
START, Device Select, RW
= 0
same as the pattern applied on Chip Enable (E0,
E1, E2).
The 8
th
bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations. If a
match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9
th
bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
Byte Write
START
DEV SEL
R/W
ACK
NO ACK
DATA IN
STOP
ACK
NO ACK
DATA IN 1
BYTE ADDR
WC
ACK
Page Write
START
DEV SEL
R/W
NO ACK
DATA IN 3
BYTE ADDR
DATA IN 2
WC (cont'd)
NO ACK
Page Write
(cont'd)
NO ACK
DATA IN N
STOP
AI02803C
5/15
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
