MITSUBISHI MICROCOMPUTERS
M35071-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
DESCRIPTION
The M35071-XXXSP/FP is a character pattern display control IC can
display on the CRT display the liquid crystal display and the plasma
display. It can display 2 pages (24 characters
×
12 lines per 1 page)
at the same time. It uses a silicon gate CMOS process and it housed
in a 20-pin shrink DIP package (M35071-XXXSP) or a 20-pin shrink
SOP package (M35071-XXXFP).
For M35071-002SP/FP that is a standard ROM version of M35071-
XXXSP/FP respectively, the character pattern is also mentioned.
PIN CONFIGURATION (TOP VIEW)
CPOUT
←
1
V
SS2
2
20
AC
→
3
TEST
→
4
SCL
→
5
SDA
↔
6
TCK
→
7
V
DD1
8
P6
←
9
P7
←
10
V
DD2
←
VERT
19
18
←
HOR
17
→
P5/B
16
→
P4
15
→
P3/G
14
→
P2
13
→
P1/R
12
→
P0/BLNK0
11
V
SS1
M35071 - XXXSP
FEATURES
•
Screen composition ................ 24 characters
×
12 lines
×
2 pages
•
Number of characters displayed .................. 288 (Max.)
×
2 pages
•
Character composition ..................................... 12
×
18 dot matrix
•
Characters available ................................ page 0 : 256 characters
•
•
•
•
•
page 1 : 128 characters
Character sizes available ................... 4 (vertic al)
×
2 (horizontal)
Display locations available
Horizontal direction .............................................. 2007 locations
Vertical direction .................................................. 1023 locations
Blinking .................................................................. Character units
Cycle : division of vertical synchronization signal into 32 or 64
Duty : 25%, 50%, or 75%
Data input ............................. By the I
2
C-BUS serial input function
Coloring
Character color ..................................................... Character unit
Background coloring ............................................. Character unit
Border (shadow) coloring ........................ 8 colors (RGB output)
Specified by register
Raster coloring ........................................ 8 colors (RGB output)
Specified by register
Blanking
Character size blanking
Border size blanking
Matrix-outline blanking
All blanking (all raster area)
Output ports
4 shared output ports (toggled between RGB output)
4 dedicated output ports
Display RAM erase function
Display input frequency range ............... F
OSC
= 20MHz to 90MHz
Horizontal synchronous input frequency
........................................................ H.sync = 15 kHz to 130 kHz
Display oscillation stop function
Outline 20P4B
CPOUT
←
1
V
SS2
2
AC
→
3
TEST
→
4
SCL
→
5
SDA
↔
6
TCK
→
7
V
DD1
8
P6
←
9
P7
←
10
20
V
DD2
19
←
VERT
18
←
HOR
17
→
P5/B
16
→
P4
15
→
P3/G
14
→
P2
13
→
P1/R
12
→
P0/BLNK0
11
V
SS1
Outline 20P2Q-A
M35071 - XXXFP
•
•
•
•
•
•
APPLICATION
CRT display, Liquid crystal display, Plasma display
REV.1.1
MITSUBISHI MICROCOMPUTERS
M35071-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
PIN DESCRIPTION
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol
CPOUT
V
SS2
__
Pin name
Filter output
Earthing pin
Auto-clear input
Test input
Clock input
Data I/O
External clock
Power pin
Port P6 output
Port P7 output
Earthing pin
Port P0 output
Port P1 output
Port P2 output
Port P3 output
Port P4 output
Port P5 output
Horizontal synchro-
nous signal input
Vertical synchro-
nous signal input
Power pin
Input/
Output
Output
–
Input
Input
Input
I/O
Input
–
Output
Output
–
Output
Output
Output
Output
Output
Output
Input
Input
–
Function
Filter output. Connect loop filter to this pin.
Connect to GND.
When “L”, this pin resets the internal IC circuit. Hysteresis input. Built-in pull-up resistor.
Test pin. Connect to +5V.
SDA pin serial data is taken in when SCL rises. Hysteresis input.
This is the pin for serial input of display control register and display RAM data. Also, this
pin output acknowledge signal. Hysteresis input. Nch opendrain output.
This is the pin for external clock input.
Please connect to +5V with the power pin.
This is the output port.
This is the output port.
Please connect to GND using circuit earthing pin.
This pin can be toggled between port pin output and BLNK0 signal output.
This pin can be toggled between port pin output and R signal output.
This is the output port.
This pin can be toggled between port pin output and G signal output.
This is the output port.
This pin can be toggled between port pin output and B signal output.
This pin inputs the horizontal synchronous signal. Hysteresis input.
This pin inputs the vertical synchronous signal. Hysteresis input.
Please connect to +5V with the power pin.
AC
TEST
SCL
SDA
TCK
V
DD1
P6
P7
V
SS1
P0/BLNK0
P1/R
P2
P3/G
P4
P5/B
HOR
VERT
V
DD2
2
BLOCK DIAGRAM
TCK
CPOUT
1
18
19
HOR
VERT
7
SCL
Clock oscillation
circuit display
Polarity switching circuit
5
Input control circuit
SDA
Synchronous signal
switching circuit
6
12 P0/BLNK0
V
DD1
H counter
8
Data control
circuit
Timing generator
Address control
circuit
13 P1/R
V
DD2
20
Display location
detection circuit
15 P3/G
Polarity switching circuit
V
SS1
11
Display control
register
17 P5/B
V
SS2
2
AC
3
TEST
Reading address
control circuit
Blinking circuit
4
Display RAM 0
(page 0)
Display RAM 1
(page 1)
14 P2
16 P4
Port output
control circuit
Shift register
Display control
circuit
9
P6
Display character
ROM 0
(page 0)
Display character
ROM 1
(page 1)
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
M35071-XXXSP/FP
10 P7
MITSUBISHI MICROCOMPUTERS
3
MITSUBISHI MICROCOMPUTERS
M35071-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
MEMORY CONSTITUTION
Address 000
16
to 11F
16
are assigned to the display RAM, address
120
16
to 128
16
are assigned to the display control registers. The in-
ternal circuit is reset and all display control registers (address 120
16
__
to 128
16
) are set to “0” when the AC pin level is “L”. And then, RAM
is not erased and be undefinited. This memory is consisted of 2
pages : page 0 memory and page 1 memory (their addresses are
common), page controlled by DAF bit of each address when writing
data. For detail, see “Data input”. Memory constitution is shown in
Figure 1 and 2.
Addresses
000
16
001
16
………
11E
16
11F
16
120
16
121
16
122
16
123
16
124
16
125
16
126
16
127
16
128
16
4
DAF
0
0
………
0
0
0
0
0
0
0
0
0
0
0
DAE
BB
BB
DAD
BG
BG
DAC
BR
BR
DAB
BLINK
BLINK
Blink-
ing
DAA
B
B
DA9
G
G
DA8
R
R
DA7
C7
C7
DA6
C6
C6
DA5
C5
C5
DA4
C4
C4
DA3
C3
C3
DA2
C2
C2
DA1
C1
C1
DA0
C0
C0
Background
coloring
BB
BB
EXCK0
BG
BG
VJT
BR
BR
Character color
Character code
BLINK
BLINK
B
B
G
G
DIV9
R
R
DIV8
C7
C7
DIV7
C6
C6
DIV6
C5
C5
DIV5
C4
C4
DIV4
C3
C3
DIV3
C2
C2
DIV2
C1
C1
DIV1
C0
C0
DIV0
DIVS1 DIVS0 DIV10
RSEL0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
RSEL1 SPACE2 SPACE1 SPACE0 HP10
EXCK1 TEST3 TEST2 TEST1 TEST0
HP9
VP9
HP8
VP8
HP7
VP7
HP6
VP6
HP5
VP5
HP4
VP4
HP3
VP3
HP2
VP2
HP1
VP1
HP0
VP0
TEST9 TEST5 TEST4 DSP11 DSP10 DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0
TEST10 VSZ1H1 VSZ1H0 VSZ1L1 VSZ1L0 V1SZ1 V1SZ0 LIN9
LIN8
LIN7
LIN6
LIN5
LIN4
LIN3
LIN2
POPUP VSZ2H1 VSZ2H0 VSZ2L1 VSZ2L0 V18SZ1 V18SZ0 LIN17 LIN16 LIN15 LIN14 LIN13 LIN12 LIN11 LIN10
MODE0 TEST12 HSZ20 TEST11 HSZ10 BETA14 TEST8 TEST7 TEST6
MODE1 BLINK2 BLINK1 BLINK0 DSPON STOP RAMERS SYAD BLK1
FB
FG
FR
RB
RG
B/F
RR
BCOL
BLK0 POLH POLV VMASK
Fig. 1 Memory constitution (page 0 memory)
MITSUBISHI MICROCOMPUTERS
M35071-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
Addresses
000
16
001
16
………
11E
16
11F
16
120
16
121
16
122
16
123
16
124
16
125
16
126
16
127
16
128
16
DAF
1
1
………
1
1
1
1
1
1
1
1
1
1
1
DAE
BB
BB
DAD
BG
BG
DAC
BR
BR
DAB
BLINK
BLINK
Blink-
ing
DAA
B
B
DA9
G
G
DA8
R
R
DA7
0
0
………
DA6
C6
C6
DA5
C5
C5
DA4
C4
C4
DA3
C3
C3
DA2
C2
C2
DA1
C1
C1
DA0
C0
C0
Background
coloring
BB
BB
–
–
–
–
–
–
–
–
–
BG
BG
–
–
BR
BR
–
–
Character color
Character code
BLINK
BLINK
–
–
B
B
–
–
G
G
–
–
HP9
VP9
R
R
–
–
HP8
VP8
0
0
–
–
HP7
VP7
C6
C6
–
–
HP6
VP6
C5
C5
–
–
HP5
VP5
C4
C4
–
–
HP4
VP4
C3
C3
–
–
HP3
VP3
C2
C2
–
–
HP2
VP2
C1
C1
–
–
HP1
VP1
C0
C0
–
–
HP0
VP0
SPACE2 SPACE1 SPACE0 HP10
TEST3 TEST2 TEST1 TEST0
–
TEST4 DSP11 DSP10 DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0
LIN8
LIN7
LIN6
LIN5
LIN4
LIN3
LIN2
VSZ1H1 VSZ1H0 VSZ1L1 VSZ1L0 V1SZ1 V1SZ0 LIN9
VSZ2H1 VSZ2H0 VSZ2L1 VSZ2L0 V18SZ1 V18SZ0 LIN17 LIN16 LIN15 LIN14 LIN13 LIN12 LIN11 LIN10
TEST12 HSZ20 TEST11 HSZ10 BETA14 TEST8 TEST7 TEST6
BLINK2 BLINK1 BLINK0 DSPON TEST13 RAMERS SYAD BLK1
FB
BLK0
FG
–
FR
–
RB
–
RG
–
RR
BCOL
Fig. 2 Memory constitution (page 1 memory)
Note: Page 0 and page 1 registers are found in their respective pages. For example, HP10 to HP0 of the page 0 memory sets the horizontal
display start position of page 0, whereas HP10 to HP0 (same register name) of the page 1 memory sets the horizontal display start
position of page 1. Also, registers common to both page 0 and page 1 are found only in the page 0 memory. For example, PTC0 is the
control register of the P0 pin and is found only in the page 0 memory.
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