M35080
8 Kbit Serial SPI Bus EEPROM
With Incremental Registers
PRELIMINARY DATA
s
Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
Single Supply Voltage: 4.5 V to 5.5 V
5 MHz Clock Rate (maximum)
Sixteen 16-bit Incremental Registers
BYTE and PAGE WRITE (up to 32 Bytes)
(except for the Incremental Registers)
Self-Timed Programming Cycle
Hardware Protection of the Status Register
Resizeable Read-Only EEPROM Area
Enhanced ESD Protection
1 Million Erase/Write Cycles (minimum)
40 Year Data Retention (minimum)
s
s
s
s
8
1
PSDIP8 (BN)
0.25 mm frame
s
s
s
s
s
s
8
1
SO8 (MN)
150 mil width
DESCRIPTION
The M35080 device consists of 1024x8 bits of low
power
EEPROM,
fabricated
with
STMicroelectronics’ proprietary High Endurance
Double Polysilicon CMOS technology.
The device is accessed by a simple SPI-compati-
ble serial interface. The bus signals consist of a
serial clock input (C), a serial data input (D) and a
serial data output (Q), as shown in Table 1.
The device is selected when the chip select input
(S) is held low. Data is clocked in during the low to
high transition of the clock, C. Data is clocked out
during the high to low transition of the clock.
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
C
D
Q
S
W
V
CC
V
SS
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Supply Voltage
Ground
D
C
M35080
S
W
Q
VSS
AI02143
June 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/18
M35080
Figure 2. DIP and SO Connections
SIGNAL DESCRIPTION
Serial Output (Q)
The output pin is used to transfer data serially out
of the Memory. Data is shifted out on the falling
edge of the serial clock.
Serial Input (D)
The input pin is used to transfer data serially into
the device. Instructions, addresses, and the data
to be written, are each received this way. Input is
latched on the rising edge of the serial clock.
Serial Clock (C)
The serial clock provides the timing for the serial
interface (as shown in Figure 3). Instructions, ad-
dresses, or data are latched, from the input pin, on
the rising edge of the clock input. The output data
on the Q pin changes state after the falling edge of
the clock input.
Chip Select (S)
When S is high, the memory device is deselected,
and the Q output pin is held in its high impedance
state. Unless an internal write operation is under-
way, the memory device is placed in its stand-by
power mode.
After power-on, a high-to-low transition on S is re-
quired prior to the start of any operation.
Write Protect (W)
The protection features of the memory device are
summarized in Table 3.
The hardware write protection, controlled by the W
pin, restricts write access to the Status Register
M35080
VSS
S
W
Q
1
2
3
4
8
7
6
5
AI02144B
VCC
D
C
NC
Note: 1. NC = Not Connected.
The memory is organized in pages of 32 bytes.
However, the first page is not treated in the same
way as the others. Instead, it is considered to con-
sist of sixteen 16-bit incremental registers. Each
register can be modified using the conventional
write instructions, but the new value will only be
accepted if it is greater than the current value.
Thus, each register is restricted to being modified
monotonically upwards.
This is useful in applications where it is necessary
to implement a counter that is protected from
fraudulent tampering (such as in a car odometer,
an electricity meter, or a tally for remaining credit).
Table 2. Absolute Maximum Ratings
1
Symbol
T
A
T
STG
T
LEAD
V
O
V
I
V
CC
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature during Soldering
Output Voltage Range
Input Voltage Range
Supply Voltage Range
Electrostatic Discharge Voltage (Human Body model)
2
Electrostatic Discharge Voltage (Machine model)
3
PSDIP8: 10 sec
SO8: 40 sec
Value
-40 to 125
-65 to 150
260
215
-0.3 to V
CC
+0.6
-0.3 to 6.5
-0.3 to 6.5
4000
400
Unit
°C
°C
°C
V
V
V
V
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and
other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500W).
3. EIAJ IC-121 (Condition C) (200pF, 0W).
2/18
M35080
Table 3. Write Protection Control
W
0 or 1
1
0
SRWD
Bit
0
1
1
Data Bytes
Mode
Software
Protected
(SPM)
Hardware
Protected
(HPM)
Status Register
Protected Area
Writeable (if the WREN
instruction has set the
WEL bit)
Hardware write protected
Software write protected
by the BP0 and BP1 bits
of the status register
Hardware write protected
by the BP0 and BP1 bits
of the status register
Unprotected Area
Writeable (if the WREN
instruction has set the
WEL bit)
Writeable (if the WREN
instruction has set the
WEL bit)
(though not to the WIP and WEL bits, which are
set or reset by the device’s internal logic).
Bit 7 of the status register (as shown in Table 4) is
the Status Register Write Disable bit (SRWD).
When this is set to 0 (its initial delivery state) it is
possible to write to the status register if the WEL
bit (Write Enable Latch) has been set by the
WREN instruction (irrespective of the level being
applied to the W input).
When bit 7 (SRWD) of the status register is set to
1, the ability to write to the status register depends
on the logic level being presented at pin W:
– If W pin is high, it is possible to write to the sta-
tus register, after having set the WEL bit using
the WREN instruction (Write Enable Latch).
– If W pin is low, any attempt to modify the status
register is ignored by the device, even if the
WEL bit has been set. As a consequence, all the
data bytes in the EEPROM area, protected by
the BP1 and BP0 bits of the status register, are
also hardware protected against data corrup-
tion, and appear as a Read Only EEPROM area
for the microcontroller. This mode is called the
Hardware Protected Mode (HPM).
It is possible to enter the Hardware Protected
Mode (HPM) either by setting the SRWD bit after
pulling low the W pin, or by pulling low the W pin
after setting the SRWD bit.
The only way to abort the Hardware Protected
Mode, once entered, is to pull high the W pin.
If W pin is permanently tied to the high level, the
Hardware Protected Mode is never activated, and
the memory device only allows the user to protect
a part of the memory, using the BP1 and BP0 bits
of the status register, in the Software Protected
Mode (SPM).
IMPORTANT:
if W pin is left floating, not driven by
the application, W is read as a logical ’0’.
Table 4. Status Register Format
b7
SRWD
UV
X
INC
BP1
BP0
WEL
b0
WIP
Note: 1. BP0, BP1: Read and write bits
2. UV, INC, WEL, WIP: Read only bits.
3. SRWD: Read and Write bit.
Figure 3. Data and Clock Timing
CPOL
CPHA
0
0
C
1
1
C
D or Q
MSB
LSB
AI01438
3/18
M35080
Figure 4. EEPROM and SPI Bus
SPI Interface with
(CPOL, CPHA) =
('0', '0') or ('1', '1')
D
Q
C
Master
(ST6, ST7, ST9,
ST10, Others)
C Q D
M35xxx
C Q D
M35xxx
S
C Q D
M35xxx
S
CS3
CS2
CS1
S
AI02148C
OPERATIONS
All instructions, addresses and data are shifted se-
rially in and out of the chip (along the bus, as
shown in Figure 4). The most significant bit is pre-
sented first, with the data input (D) sampled on the
first rising edge of the clock (C) after the chip se-
lect (S) goes low (as shown in Figure 5, Figure 9,
and Figure 12).
Every instruction, as summarized in Table 5, starts
with a single-byte code. If an invalid instruction is
sent (one not contained in Table 5), the chip auto-
matically deselects itself.
The instruction code is entered via the data input
(D), and latched on the rising edge of the clock in-
put (C). To enter an instruction code, the device
must have been previously selected (S held low).
Protection of the First 32 Bytes
The first 32-byte page is organized as 16 words
(two bytes each). The initial content of each word
on this page is 0000h. When writing to byte-pair, a
logic comparator verifies that the new two-byte
value is larger than the value currently stored. If
the new value is smaller than the current one, no
operation is performed. It is impossible to write a
value lower than the previous one, irrespective of
the state of W pin and status register, as indicated
in Table 6.
Write Enable (WREN) and Write Disable (WRDI)
The write enable latch, inside the memory device,
must be set prior to each WRITE and WRSR oper-
ation. The WREN instruction (write enable) sets
this latch, and the WRDI instruction (write disable)
resets it.
Table 5. Instruction Set
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
WRINC
Description
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Write Data to Secure Array
Instruction Format
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
0000 0111
4/18
M35080
Figure 5. Read EEPROM Array Operation Sequence
S
0
C
INSTRUCTION
16 BIT ADDRESS
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30
D
HIGH IMPEDANCE
Q
15 14 13
3
2
1
0
DATA OUT
7
MSB
AI01793
6
5
4
3
2
1
0
Note: 1. The most significant address bits, A15-A10, are treated as Don’t Care.
The latch becomes reset by any of the following
events:
– Power on
– WRDI instruction completion
– WRSR instruction completion
– WRITE instruction completion.
As soon as the WREN or WRDI instruction is re-
ceived, the memory device first executes the in-
struction, then enters a wait mode until the device
is deselected.
Read Status Register (RDSR)
The RDSR instruction allows the status register to
be read, and can be sent at any time, even during
a Write operation. Indeed, when a Write is in
progress, it is recommended that the value of the
Write-In-Progress (WIP) bit be checked. The value
in the WIP bit (whose position in the status register
is shown in Table 4) can be continuously polled,
before sending a new WRITE instruction. This can
be performed in one of two ways:
s
Repeated RDSR instructions (each one
consisting of S being taken low, C being clocked
8 times for the instruction and 8 times for the
read operation, and S being taken high)
s
A single, prolonged RDSR instruction
(consisting of S being taken low, C being
clocked 8 times for the instruction and kept
running for repeated read operations), as
shown in Figure 6.
The Write-In-Process (WIP) bit is read-only, and
indicates whether the memory is busy with a Write
operation. A ’1’ indicates that a write is in progress,
and a ’0’ that no write is in progress.
The Write Enable Latch (WEL) bit indicates the
status of the write enable latch. It, too, is read-only.
Its value can only be changed by one of the events
listed earlier, or as a result of executing WREN or
WRDI instruction. It cannot be changed using a
WRSR instruction. A ’1’ indicates that the latch is
set (the forthcoming Write instruction will be exe-
cuted), and a ’0’ that it is reset (and any forthcom-
ing Write instructions will be ignored).
The Block Protect (BP0 and BP1) bits indicate the
amount of the memory that is to be write-protect-
ed. These two bits are non-volatile. They are set
using a WRSR instruction.
During a Write operation (whether it be to the
memory area or to the status register), all bits of
the status register remain valid, and can be read
using the RDSR instruction. However, during a
Write operation, the values of the non-volatile bits
Table 6. Memory Mapping
Address
000h-01Fh
020h-3FFh
Protection
Incremental area: a word (2 bytes) can be written only if the new value to write is larger
than the value already stored
No specific protection except the one as of Table 7
5/18
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