MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
DESCRIPTION/FEATURES
•
High-breakdown-voltage output port ......................................... 26
• Segment output ............................................ 8 to 18
• Digit output ................................................... 7 to 10
(Ports P0 to P7 are also used as ordinary output ports)
• Output breakdown .................................. Vcc – 45 V
• Output current .................. –18 mA (DIG
0
to DIG
17
),
–7 mA (SEG
0
to SEG
7
)
• Pull-down resistor ........................................ build-in
• Dimmer switch ............................................ 4 levels
A-D converter ................................................... 8-bit
!
6 channels
• Absolute accuracy ....................................... ±3 LSB
•
Serial I/O ..................................... 4 (CS controller, external clock)
• Noise filter .................................................... build-in
(in serial input pin and clock pin, 2 MHz sampling)
• FLD display data ............................................. input
• A-D conversion data ..................................... output
• Command ....................................................... input
Package ................................................................. 44P6N/44P6X
Oscillating circuit ........... RC oscillating cirucit (external capacitor)
• Oscillating frequency ..................................... 4 MHz
Power source voltage .................................................. 4.0 to 5.5 V
•
•
•
•
PIN CONFIGURATION (TOP VIEW)
DIG
15
/SEG
10
DIG
14
/SEG
11
DIG
13
/SEG
12
DIG
12
/SEG
13
DIG
11
/SEG
14
DIG
10
/SEG
15
DIG
9
/SEG
16
DIG
8
/SEG
17
DIG
7
/P7
25
DIG
6
/P6
24
33
32
31
30
29
28
27
26
DIG
16
/SEG
9
DIG
17
/SEG
8
SEG
7
SEG
6
SEG
5
SEG
4
SEG
3
SEG
2
SEG
1
SEG
0
V
DD
23
DIG
5
/P5
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
DIG
4
/P4
DIG
3
/P3
DIG
2
/P2
DIG
1
/P1
DIG
0
/P0
V
EE
V
EE
S
CLK
S
OUT
S
IN
CS
M35500AFP
M35500BGP
V
DD
V
SS
X
IN
RESET
AN
5
AN
4
AN
3
AN
2
AN
1
Package type: 44P6N-A/44P6X
Fig. 1. Pin configuration of M35500AFP/BGP
X
OUT
AN
0
1
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
FUNCTIONAL BLOCK
DIG
8
/SEG
17
– DIG
17
/SEG
8
SEG
7
– SEG
0
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DIG
7
/P7
25
DIG
6
/P6
24
DIG
5
/P5
23
DIG
4
/P4
22
DIG
3
/P3
21
DIG
2
/P2
20
DIG
1
/P1
19
DIG
0
/P0
18
V
EE 17
V
EE 16
Memory
address
Display RAM
Transfer
counter
Mode
register
Display control circuit
FUNCTIONAL BLOCK DIAGRAM (Package: 44P6N-A)
Command
analytic circuit
Byte end
CS
12
S
IN 13
S
OUT 14
S
CLK 15
V
DD 44
V
DD 1
V
SS 3
RESET
5
2
4
6
7
8
9
10 11
Noise filter
Noise filter
Trigger
Clock generating
circuit
Selector/A-D
control circuit
Serial I/O
A-D
X
OUT
X
IN
AN
5
– AN
0
Fig. 2. Functional block diagram
2
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
PIN DESCRIPTION
Table. 1. Pin description
Pin
V
CC
, V
SS
V
EE
X
IN
X
OUT
______
Name
Power source
Pull-down
power source
Clock input
Clock output
______
Input
Output
Function
• Apply voltage of 5 V to V
CC
, and 0 V to V
SS
.
• Applies voltage supplied to pull-down resistors.
Input
Output
CMOS input
CMOS input
CMOS input
Noise filter
N-channel
open-drain
CMOS input
Noise filter
P-channel
open-drain
P-channel
open-drain
P-channel
open-drain
• RC oscillator pins for system clock.
RESET
____
RESET input
Chip select
Serial clock
Serial output
Serial input
Digit/Port
Digit/Segment
Segment
• Reset input pin for active “L”.
• Internal pull-up resistors connected between the RESET and V
CC
pins.
• Serial transfer is possible by inputting “L” signal.
• Clock for serial transfer is input.
• Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
• Serial data is output.
• During reset it is in high-impedance state.
• Serial data is input.
• Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
• Pin for ordinary output or digit output.
• At reset this port is set to V
EE
level through a pull-down resistor.
• Pin for digit output or segment output.
• At reset this port is set to V
EE
level through a pull-down resistor.
• Pin for segment output.
• At reset this port is set to V
EE
level through a pull-down resistor.
CS
S
CLK
S
OUT
S
IN
DIG
0
/P0 –
DIG
7
/P7
DIG
8
/SEG
17
–
DIG
17
/SEG
8
SEG
0
– SEG
7
PORT BLOCK
(1) Digit/Port pin
Digit/Segment pin
Shift signal from high-order
Dimmer signal
(Note)
Data bus
Segment data
latch
V
(4) S
OUT
pin
S
OUT
signal
Shift signal to low-order
(2) Digit pin
Shift signal from high-order
Dimmer signal
(Note)
latch
(5) CS pin
V
EE
CS input
Noise filter
V
(6) S
IN
, S
CLK
pin
Serial input
Serial clock input
Noise filter
Shift signal to low-order
V
EE
(7) A-D input
(3) Segment pin
Dimmer signal
(Note)
Segment data
latch
V
A-D conversion input
V
EE
V
High-breakdown-voltage P-channel transistor
Note:
Dimmer signal is for setting the Toff time.
Fig. 3. Port block diagram
3
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
COMMAND STYLE
b7
Display data setting
(Command 0)
1
b6
1
b5
1
b4
—
b3
b2
b1
b0
Number of segment setting
0 0 : 16 or less
0 1 : 17 or more
Number of digit setting
00:7
01:8
10:9
1 1 : 10
Display state setting
(Command 1)
1
1
0
—
—
Display ON or OFF setting
1 : ON
0 : OFF
Display duty setting
1 1 : 15/16
1 0 : 14/16
0 1 : 6/16
0 0 : 5/16
Digit selection
(Command 2)
1
0
1
—
Digit start pin setting
0 0 0 0 : D
17
0 0 0 1 : D
16
0 0 1 0 : D
15
0 0 1 1 : D
14
0 1 0 0 : D
13
0 1 0 1 : D
12
0 1 1 0 : D
11
0 1 1 1 : D
10
1 0 0 0 : D
9
1 0 0 1 : D
8
1 0 1 0 : D
7
Port data setting
(Command 3)
1
0
0
P3 – P0/P7 – P4 output data
Port selection (Note)
0 : P3 – P0
1 : P7 – P4
Note:
When a digit or a port has to be selected, a digit output is selected for having higher priority.
Fig. 4. Command style
4
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
SERIAL I/O PROTOCOL
Byte protocol
CS
CLK
b0
b1
b2
b3
b4
b5
b6
b7
S
IN
S
OUT
X
b0
b1
b2
b3
b4
b5
b6
b7
Note:
S
OUT
is in high-impedance state during CS signal is “H”.
Command protocol
Display data setting
(Command 0)
CS
CLK
S
IN
S
OUT
Command 0
Data 1
Data 2
Data i
X
X
A-D
data 0
A-D
data j
Note 1:
The serial data which is transmitted after executing command 0
is recognized as a display data.
“A-D data 6 or more” data is defined as an undefined “X”.
Note 2:
Set the CS signal to “H” level after transferring a display data.
Other setting except
display data setting
(Command 1 to 3)
CS
CLK
S
IN
S
OUT
Command
X
Fig. 5. Serial I/O protocol
5
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