M368L3223CTL
184pin Unbuffered DDR SDRAM MODULE
256MB DDR SDRAM MODULE
(32Mx64 based on 32Mx8 DDR SDRAM)
Unbuffered 184pin DIMM
64-bit Non-ECC/Parity
Revision 0.3
May. 2002
Rev. 0.3 May. 2002
M368L3223CTL
Revision History
Revision 0 (Oct 2001)
1. First release for internal usage
184pin Unbuffered DDR SDRAM MODULE
Version 0.1(November,2001)
- Revised "Absolute maximum rating" table in page 38.
. Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V
. Changed "power dissipation" value from 8W to 12W.
- Revised AC parameter table
From
DDR266A
Min.
tHZ
tACmin
-400ps
tACmin
-400ps
0.25
10ns
Max.
tACmax
-400ps
tACmax
-400ps
DDR266B
Min.
tACmin
-400ps
tACmin
-400ps
0.25
10ns
Max.
tACmax
-400ps
tACmax
-400ps
DDR200
Min.
tACmin
-400ps
tACmin
-400ps
0.25
10ns
Max.
tACmax
-400ps
tACmax
-400ps
DDR266A
Min.
-0.75
Max.
+0.75
To
DDR266B
Min.
-0.75
Max.
+0.75
DDR200
Min.
-0.8
Max.
+0.8
tLZ
tWPST
(tCK)
tPDEX
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
0.4
7.5ns
0.6
0.4
7.5ns
0.6
0.4
10ns
0.6
Revision 0.2 (Jan, 2002)
1. Added tRAP(Active to Read w/ autoprecharge command)
Revision 0.3 (May, 2002)
1. Change pin location of A13 from pin 103 to pin 167
Rev. 0.3 May. 2002
M368L3223CTL
184pin Unbuffered DDR SDRAM MODULE
M368L3223CTL DDR SDRAM 184pin DIMM
32Mx64 DDR SDRAM 184pin DIMM based on 32Mx8
GENERAL DESCRIPTION
The Samsung M368L3223CTL is 32M bit x 64 Double Data
Rate SDRAM high density memory modules. The Samsung
M368L3223CTL consists of eight CMOS 32M x 8 bit with
4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)
packages mounted on a 184pin glass-epoxy substrate. Four
0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR SDRAM. The M368L3223CTL
is Dual In-line Memory Modules and inten-ded for mounting
into 184pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
FEATURE
• Performance range
Part No.
Max Freq.
Interface
SSTL_2
M368L3223CTL-C(L)B3 167MHz(6.0ns@CL=2.5)
M368L3223CTL-C(L)A2 133MHz(7.5ns@CL=2)
M368L3223CTL-C(L)B0 133MHz(7.5ns@CL=2.5)
• Power supply : Vdd: 2.5V
±
0.2V, Vddq: 2.5V
±
0.2V
•
Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB :
Height 1250 mil,
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
PIN DESCRIPTION
Pin
Back
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK0, CK0 ~ CK2, CK2
CKE0
CS0
RAS
CAS
WE
DM0 ~ DM7
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
VDDID
Pin Front Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
*CB0
*CB1
VDD
*DQS8
A0
*CB2
VSS
*CB3
BA1
KEY
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
/CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
*CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Back
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
*CB4
*CB5
VDDQ
CK0
/CK0
VSS
*DM8
A10
*CB6
VDDQ
*CB7
KEY
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Supply (2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
VDD identification flag
154
/RAS
155
DQ45
156
VDDQ
157
/CS0
158
*/CS1
159
DM5
160
VSS
161
DQ46
162
DQ47
163
*/CS3
164
VDDQ
165
DQ52
166
DQ53
167
*A13
168
VDD
169
DM6
170
DQ54
171
DQ55
172
VDDQ
173
NC
174
DQ60
175
DQ61
176
VSS
177
DM7
178
DQ62
179
DQ63
180
VDDQ
181
SA0
182
SA1
183
SA2
184 VDDSPD
NC
No connection
* These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.3 May. 2002
M368L3223CTL
Functional Block Diagram
184pin Unbuffered DDR SDRAM MODULE
DQS0
DM0
CS0
DQS4
DM4
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
D4
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
C S DQS
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D1
D5
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D2
D6
* Clock Wiring
Clock
Input
CK0/CK0
CK1/CK1
CK2/CK2
SDRAMs
2 SDRAMs
3 SDRAMs
3 SDRAMs
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D3
D7
*Clock Net Wiring
Dram1
Cap
R=120
Ω
Dram3
*(Cap)
Cap
Dram5
Cap
*If two DRAMs are loaded,
Cap will replace DRAM3
Serial PD
BA0 - BA1
A0 - A13
RAS
CAS
CKE0
WE
V
DDSPD
V
D D
/V
DDQ
BA0-BA1: SDRAMs D0 - D7
A0-A13: SDRAMs D0 - D7
RAS : SDRAMs D0 - D7
CAS : SDRAMs D0 - D7
CKE: SDRAMs D0 - D7
WE: SDRAMs D0 - D7
SPD
D0 - D7
D0 - D7
VREF
V
SS
D0 - D7
D0 - D7
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
Card
Edge
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/ CS relationships
must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 0.3 May. 2002
M368L3223CTL
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Voltage on V
DDQ
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
184pin Unbuffered DDR SDRAM MODULE
Symbol
V
IN
, V
OUT
V
DD
V
DDQ
T
STG
P
D
I
OS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
12
50
Unit
V
V
V
°C
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 70°C)
Parameter
Supply voltage(for device with a nominal V
DD
of 2.5V)
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
Output leakage current
Output High Current(Normal strengh driver)
;V
OUT
= V
T T
+ 0.84V
Output High Current(Normal strengh driver)
;V
OUT
= V
T T
- 0.84V
Output High Current(Half strengh driver)
;V
OUT
= V
T T
+ 0.45V
Output High Current(Half strengh driver)
;V
OUT
= V
T T
- 0.45V
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
I H
(DC)
V
IL
(DC)
V
I N
(DC)
V
I D
(DC)
V
IX
(DC)
I
I
I
O Z
I
OH
I
OL
I
OH
Min
2.3
2.3
VDDQ/2-50mV
V
REF
-0.04
V
REF
+0.15
-0.3
-0.3
0.3
1.15
-2
-5
-16.8
16.8
-9
Max
2.7
2.7
VDDQ/2+50mV
V
REF
+0.04
V
DDQ
+0.3
V
REF
-0.15
V
DDQ
+0.3
V
DDQ
+0.6
1.35
2
5
Unit
Note
V
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
3
5
1
2
4
4
I
OL
9
mA
Notes
1. Includes
±
25mV margin for DC offset on V
REF
, and a combined total of
±
50mV margin for all AC noise and DC offset on V
REF
,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled
TO V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of
≤
3nH.
2.V
TT
is not applied directly to the device. V
T T
is a system supply for signal termination resistors, is expected to be set equal to
V
REF
, and must track variations in the DC level of V
REF
3. V
I D
is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.3 May. 2002
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