M36W108AT
M36W108AB
8 Mbit (1Mb x8, Boot Block) Flash Memory and
1 Mbit (128Kb x8) SRAM Low Voltage Multi-Memory Product
PRELIMINARY DATA
s
SUPPLY VOLTAGE
– V
CCF
= V
CCS
= 2.7V to 3.6V: for Program,
Erase and Read
s
s
ACCESS TIME: 100ns
LOW POWER CONSUMPTION
– Read: 40mA max. (SRAM chip)
– Stand-by: 30µA max. (SRAM chip)
– Read: 10mA max. (Flash chip)
– Stand-by: 100µA max. (Flash chip)
LBGA48 (ZM)
6 x 8 solder balls
LGA48 (ZN)
6 x 8 solder lands
BGA
LGA
FLASH MEMORY
s
8 Mbit (1Mb x 8) BOOT BLOCK ERASE
s
s
PROGRAMMING TIME: 10µs typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Status Register bits and Ready/Busy Output
Figure 1. Logic Diagram
s
s
s
SECURITY PROTECTION MEMORY AREA
INSTRUCTION ADDRESS CODING: 3 digits
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main Blocks
20
A0-A19
W
EF
G
RP
E1S
E2S
M36W108AT
M36W108AB
RB
8
DQ0-DQ7
VCCF VCCS
s
s
BLOCK, MULTI-BLOCK and CHIP ERASE
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
s
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M36W108AT: D2h
– Device Code, M36W108AB: DCh
s
SRAM
s
1 Mbit (128Kb x 8)
s
VSS
AI02620
POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
LOW V
CC
DATA RETENTION: 2V
1/36
s
March 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M36W108AT, M36W108AB
Figure 2. LBGA and LGA Connections (Top View)
1
2
3
4
5
6
A
W
A14
A11
G
A10
E1S
B
VCCS
A18
A8
DQ7
DQ5
VSS
C
A17
NC
A5
DQ4
DQ2
DQ1
D
VSS
EF
NC
DQ0
A0
A1
E
NC
NC
DQ3
A6
A3
A2
F
NC
VCCF
NC
A19
A7
A4
G
NC
DQ6
A13
RP
RB
E2S
H
NC
A12
NC
A16
A15
A9
AI02508
Table 1. Signal Names
A0-A16
A17-A19
DQ0-DQ7
EF
E1S, E2S
G
W
RP
RB
V
CCF
V
CCS
V
SS
NC
Address Inputs
Address Inputs for Flash Chip
Data Input/Outputs, Command Inputs
for Flash Chip
Chip Enable for Flash Chip
Chip Enable for SRAM Chip
Output Enable
Write Enable
Reset for Flash Chip
Ready/Busy Output for Flash Chip
Supply Voltage for Flash Chip
Supply Voltage for SRAM Chip
Ground
Not Connected Internally
DESCRIPTION
The M36W108A is multi-chip device containing an
8 Mbit boot block Flash memory and a 1 Mbit of
SRAM. The device is offered in the new Chip
Scale Package solutions: LBGA48 1.0mm ball
pitch and LGA48 1.0mm land pitch.
The two components, of the package’s overall 9
Mbit of memory, are distinguishable by use of the
three chip enable lines: EF for the Flash memory,
E1S and E2S for the SRAM.
The Flash memory component is identical with the
M29W008A device. It is a non-volatile memory
that may be erased electrically at the block or chip
level and programmed in-system on a Byte-by-
Byte basis using only a single 2.7V to 3.6V V
CCF
supply. For Program and Erase operations the
necessary high voltages are generated internally.
The device can also be programmed in standard
programmers. The array matrix organization al-
lows each block to be erased and reprogrammed
without affecting other blocks.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature, Programming, Block
2/36
M36W108AT, M36W108AB
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CCF
V
CCS
V
(EF, RP)
PD
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Flash Chip Supply Voltage
SRAM Chip Supply Voltage
EF, RP Voltage
Power Dissipation
Value
–40 to 85
–50 to 125
–65 to 150
–0.5 to V
CC
+0.5
–0.6 to 5
–0.3 to 4.6
0.6 to 13.5
0.7
Unit
°C
°C
°C
V
V
V
V
W
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
and Chip Erase, Erase Suspend and Resume are
written to the device in cycles of commands to a
Command Interface using standard microproces-
sor write timings.
The SRAM component is a low power SRAM that
features fully static operation requiring no external
clocks or timing strobes, with equal address ac-
cess and cycle times. It requires a single 2.7V to
3.6V V
CCS
supply, and all inputs and outputs are
TTL compatible.
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A16).
Addresses A0 to A16
are common inputs for the Flash chip and the
SRAM chip. The address inputs for the Flash
memory or the SRAM array are latched during a
write operation on the falling edge of Flash Chip
Enable (EF), SRAM Chip Enable (E1S or E2S) or
Write Enable (W).
Address Inputs (A17-A19).
Address A17 to A19
are address inputs for the Flash chip. They are
latched during a write operation on the falling edge
of Flash Chip Enable (EF) or Write Enable (W).
Data Input/Outputs (DQ0-DQ7).
The input is
data to be programmed in the Flash or SRAM
memory array or a command to be written to the
C.I. of the Flash chip. Both are latched on the ris-
ing edge of Flash Chip Enable (EF), SRAM Chip
Enable (E1S or E2S) or Write Enable (W). The
output is data from the Flash memory or SRAM ar-
ray, the Electronic Signature Manufacturer or De-
vice codes or the Status register Data Polling bit
DQ7, the Toggle Bits DQ6 and DQ2, the Error bit
DQ5 or the Erase Timer bit DQ3. Outputs are valid
when Flash Chip Enable (EF) or SRAM Chip En-
able (E1S or E2S) and Output Enable (G) are ac-
tive. The output is high impedance when the both
the Flash chip and the SRAM chip are deselected
or the outputs are disabled and when Reset (RP)
is at a V
IL
.
Flash Chip Enable (EF).
The Chip Enable input
for Flash activates the memory control logic, input
buffers, decoders and sense amplifiers. EF at V
IH
deselects the memory and reduces the power con-
sumption to the standby level. EF can also be
used to control writing to the command register
and to the Flash memory array, while W remains
at V
IL
. It is not allowed to set EF at V
IL
, E1S at V
IL
and E2S at V
IH
at the same time.
SRAM Chip Enable (E1S, E2S).
The Chip En-
able inputs for SRAM activate the memory control
logic, input buffers, decoders and sense amplifi-
ers. E1S at V
IH
or E2S at V
IL
deselects the mem-
ory and reduces the power consumption to the
standby level. E1S and E2S can also be used to
control writing to the SRAM memory array, while
W remains at V
IL
. It is not allowed to set EF at V
IL
,
E1S at V
IL
and E2S at V
IH
at the same time.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is High the outputs are High im-
pedance.
Write Enable (W).
The Write Enable input con-
trols writing to the Command Register of the Flash
chip and Address/Data latches.
3/36
M36W108AT, M36W108AB
Table 3. Main Operation Modes
(1)
Operation Mode
Flash Chip Read
V
IL
SRAM Chip Read
Flash Chip Write
V
IL
SRAM Chip Write
Flash Chip Output Disable
X
SRAM Chip Output Disable
Flash Chip Stand-by
Flash Chip Reset
X
X
SRAM Chip Stand-by
X
Note: 1. X = V
IL
or V
IH
.
EF
V
IL
E1S
V
IH
X
V
IL
V
IH
X
V
IL
V
IH
X
V
IL
X
V
IH
X
V
IH
X
E2S
X
V
IL
V
IH
X
V
IL
V
IH
X
V
IL
V
IH
X
X
V
IL
X
V
IL
G
V
IL
V
IL
V
IL
V
IH
V
IH
X
V
IH
V
IH
V
IH
X
X
X
X
X
W
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
X
X
X
X
X
RP
V
IH
V
IH
X
V
IH
V
IH
X
X
X
X
V
IH
V
IL
V
IL
V
IL
V
IL
DQ7-DQ0
Data Output
Data Output
Data Output
Data Input
Data Input
Data Input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
V
IH
V
IL
V
IH
X
V
IH
V
IH
X
Reset Input (RP).
The Reset input provides
hardware reset of the Flash chip. Reset of the
Flash memory is achieved by pulling RP to V
IL
for
at least t
PLPX
. When the reset pulse is given, if the
Flash memory is in Read or Standby modes, it will
be available for new operations in t
PHEL
after the
rising edge of RP.
If the Flash memory is in Erase or Program mode
the reset will take t
PLYH
during which the Ready/
Busy (RB) signal will be held at V
IL
. The end of the
Flash memory reset will be indicated by the rising
edge of RB. A hardware reset during an Erase or
Program operation will corrupt the data being pro-
grammed or the block(s) being erased. See Table
18 and Figure 10.
Ready/Busy Output (RB).
Ready/Busy is an
open-drain output of the Flash chip. It gives the in-
ternal state of the Program/Erase Controller (P/
E.C.) of the Flash device. When RB is Low, the
Flash device is busy with a Program or Erase op-
eration and it will not accept any additional pro-
gram or erase instructions except the Erase
Suspend instruction. When RB is High, the Flash
device is ready for any Read, Program or Erase
operation. The RB will also be High when the
Flash memory is put in Erase Suspend or Standby
modes.
V
CCF
Supply Voltage.
Flash memory power sup-
ply for all operations (Read, Program and Erase).
V
CCS
Supply Voltage.
SRAM power supply for
all operations (Read, Program).
V
SS
Ground.
V
SS
is the reference for all voltage
measurements.
POWER SUPPLY
Power Up.
The Flash memory Command Inter-
face is reset on power up to Read Array. Either
Flash Chip Enable (EF) or Write Enable (W) inputs
must be tied to V
IH
during Power Up to allow max-
imum security and the possibility to write a com-
mand on the first rising edge of EF and W. Any
write cycle initiation is blocked when V
CCF
is below
V
LKO
.
Supply Rails.
Normal precautions must be taken
for supply voltage decoupling; each device in a
system should have the V
CCF
, V
CCS
rails decou-
pled with a 0.1µF capacitor close to the V
CCF
,
V
CCS
and V
SS
pins. The PCB trace widths should
be sufficient to carry the V
CCF
and V
CCS
program
currents and the V
CCF
erase current required.
4/36
M36W108AT, M36W108AB
Figure 3. Internal Functional Arrangement
VCCF
VSS
RP
EF
A0-A19
8 Mbit
Flash Memory
(1Mb x 8)
RB
DQ0-DQ7
W
G
VCCS
VSS
A0-A16
1 Mbit SRAM
(128 Kb x 8)
E1S
E2S
AI02444
5/36
NXP MCU
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