This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated
voltages to this high impedance circuit.
MB814100C-60
MB814100C-70
Fig. 1 – MB814100C DYNAMIC RAM – BLOCK DIAGRAM
RAS
CAS
Mode
Control
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
Refresh
Address
Counter
Substrate
Bias Gen
Address
Buffer
&
Pre–
Decoder
Row
Decoder
CAPACITANCE
(T
A
= 25°C, f = 1MHz)
Parameter
Input Capacitance, A0 to A10, DIN
Input Capacitance, RAS, CAS, WE
Output Capacitance, DOUT
Symbol
C
IN1
C
IN2
C
OUT
Typ
—
—
—
Max
5
7
7
Unit
pF
pF
pF
2
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
– PRELIMINARY –
Edition 2.0
Clock
Gen #1
Write
Clock
Gen
WE
Clock
Gen #2
Data In
Buffer
DIN
Column
Decoder
Sense Ampl &
I/O Gate
• • •
•
•
•
4,194,304 Bit
Storage
Cell
Data Out
Buffer
DOUT
V
CC
V
SS
PIN ASSIGNMENTS AND DESCRIPTIONS
26–Pin SOJ:
(TOP VIEW)
<LCC–26P–M04>
<Normal Bend : FPT–26P–M01>
D IN
WE
RAS
NC.
A 10
1
2
3
4
5
26
25
24
23
22
V
SS
DOUT
CAS
NC.
A9
RAS
NC.
A 10
D IN
WE
1
2
3
4
5
26
25
24
23
22
VSS
DOUT
CAS
NC.
A9
A0
A1
A2
A3
V
CC
9
10
11
12
13
Designator
D IN
D OUT
WE
RAS
NC
A0 to A10
VCC
CAS
VSS
Function
Data Input.
Data Output.
Write Enable.
Row address strobe.
No connection.
Address inputs.
+5 volt power supply.
Column address strobe.
Circuit ground.
A
A
A
8
7
6
18
17
16
15
14
9
10
11
12
13
A0
A1
A2
A3
V
CC
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
– PRELIMINARY –
Edition 2.0
26–Pin FPT:
(TOP VIEW)
18
17
16
15
14
A
A
A
8
7
6
A0
A1
A2
A3
V
CC
9
10
11
12
13
18
17
16
15
14
A
A
A
A5
A4
<Reverse Bend : FPT–26P–M02>
VSS
D OUT
CAS
NC.
A9
26
25
24
23
22
1
2
3
4
5
A5
A4
MB814100C-60
MB814100C-70
8
7
6
A5
A4
D IN
WE
RAS
NC.
A 10
3
MB814100C-60
MB814100C-70
RECOMMENDED OPERATING CONDITIONS
Parameter
Notes
Symbol
V
CC
Supply Voltage
1
V
SS
Input High Voltage, all inputs
Input Low Voltage, all inputs
*
1
1
VIH
VIL
0
2.4
–0.3
0
—
—
0
6.5
0.8
V
V
Min
4.5
Typ
5.0
Max
5.5
V
0
°
C to +70
°
C
Unit
Ambient
Operating Temp
* :
Undershoots of up to –2.0 volts with a pulse width not exceeding 20ns are acceptable.
FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty–two input bits are required to decode any one of 4,194,304 cell addresses in the memory matrix. Since only eleven address bits (A0–A10) are
available, the column and row inputs are separately strobed by RAS and CAS as shown in Figure 5. First, eleven row address bits are applied on pins
A0–through–A10 and latched with the row address strobe (RAS) then, eleven column address bits are applied and latched with the column address
strobe (CAS). Both row and column addresses must be stable on or before the falling edge of RAS and CAS, respectively. The address latches are of
the flow–through type; thus, address information appearing after t
RAH
(min)+ t
T
is automatically treated as the column address.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated; when WE is High, a read cycle is
selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of two basic ways––an early write cycle and a read–modify–write cycle. The falling edge of WE or CAS,
whichever is later, serves as the input data–latch strobe. In an early write cycle, the input data is strobed by CAS and the setup/hold times are
referenced to CAS because WE goes Low before CAS. In a delayed write or a read–modify–write cycle, WE goes Low after CAS; thus, input data is
strobed by WE and all setup/hold times are referenced to the write–enable signal.
DATA OUTPUT
The three–state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical to that of the input; the output buffers
remain in the high–impedance state until the column address strobe goes Low. When a read or read–modify–write cycle is executed, valid outputs are
obtained under the following conditions:
t
RAC
:
from the falling edge of RAS when t
RCD
(max) is satisfied.
t
CAC
:
t
AA
:
from the falling edge of CAS when t
RCD
is greater than t
RCD
(max).
from column address input when t
RAD
is greater than t
RAD
(max).
The data remains valid until either CAS returns to a High logic level. When an early write is executed, the output buffers remain in a high–impedance
state during the entire cycle.
FAST PAGE MODE OF OPERATION
The fast page mode of operation provides faster memory access and lower power dissipation. The fast page mode is implemented by keeping the
same row address and strobing in successive column addresses. To satisfy these conditions, RAS is held Low for all contiguous memory cycles in
which row addresses are common. For each fast page of memory, any of 2,048–bits can be accessed and, when multiple MB 814100As are used,
CAS is decoded to select the desired memory fast page. Fast page mode operations need not be addressed sequentially and combinations of read,
write, and/or ready–modify–write cycles are permitted.
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