Product Specification
PE4235
Product Description
The PE4235 RF Switch is designed to cover a broad range of
applications from near DC to 4000 MHz. This single-supply
reflective switch integrates on-board CMOS control logic
driven by a simple, single-pin CMOS or TTL control input.
Using a nominal +3-volt power supply, a 1 dB compression
point of +15 dBm can be achieved. The PE4235 also exhibits
outstanding isolation of better than 40 dB at 1000 MHz and is
offered in a small 3x3 mm DFN package.
The PE4235 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Diagram
RFC
SPDT UltraCMOS™ RF Switch
DC - 4000 MHz
Features
•
Single 3.0-volt power supply
•
Low insertion loss: 0.40 dB at
1000 MHz, 0.45 dB at 2000 MHz
•
High isolation of 40 dB at 1000 MHz,
30 dB at 2000 MHz
•
Typical 1 dB compression point of
+15 dBm
•
Single-pin CMOS or TTL logic control
•
Available in a 6-lead DFN package
Figure 2. Package Type
6-lead DFN
RF1
RF2
CMOS
Control
Driver
CTRL
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3 V
(ZS = ZL = 50
Ω)
Parameter
Operating Frequency
1
Insertion Loss
Isolation – RFC to RF1/RF2
Isolation – RF1 to RF2
Return Loss
‘ON’ Switching Time
‘OFF’ Switching Time
Video Feedthrough
2
Input 1 dB Compression
Input IP3
2000 MHz
2000 MHz, 5 dBm
13.5
32.5
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
CTRL to 0.1 dB final value, 2 GHz
CTRL to 25 dB isolation, 2 GHz
39
29
36
28
20
17
Conditions
Minimum
DC
Typical
0.40
0.45
40
30
37
29
22
19
200
90
2.5
15
36
Maximum
4000
0.50
0.60
Units
MHz
dB
dB
dB
dB
dB
dB
dB
dB
ns
ns
mV
pp
dBm
dBm
Notes: 1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to
High or High to Low in a 50
Ω
test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
Document No. 70-0069-04
│
www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 8
PE4235
Product Specification
Figure 3. Pin Configuration
RF2
GND
RF1
1
2
3
Exposed Solder
Pad - Shorted
to Pin 2
(bottom side)
Table 4. Absolute Maximum Ratings
Symbol
Parameter/Conditions
Power Supply Voltage
Voltage on any input
except for CTRL pin
Voltage on CTRL pin
Storage temperature range
Operating temperature
range
Input power (50
Ω)
ESD Voltage (Human Body
Model)
-65
-40
Min
-0.3
-0.3
Max
4.0
V
DD
+ 0.3
5
150
85
19
200
Units
V
V
V
°C
°C
dBm
V
6
5
4
RFC
CTRL
V
DD
V
I
V
CTRL
T
ST
V
DD
T
OP
P
IN
Table 2. Pin Descriptions
Pin
No.
1
V
ESD
Pin
Name
RF2
RF2 port.
1
Description
2
GND
Ground Connection. Traces should be
physically short and connected to the
ground plane. This pin is connected to
the exposed solder pad that also must
be soldered to the ground plane for best
performance.
RF1 port.
1
Nominal 3 V supply connection.
CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
Common RF port for switch.
1
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Control Logic Input
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal. For
flexibility to support systems that have 5-volt
control logic drivers, the control logic input has
been designed to handle a standard 5-volt TTL
control signal. This TTL control signal input must
not exceed 5-volts or damage to the switch could
result.
Table 5. Control Logic Truth Table
Control Voltage
Signal Path
RFC to RF1
RFC to RF2
3
4
RF1
V
DD
5
CTRL
6
RFC
Notes: 1.
All RF pins must be DC blocked with an external series
capacitor or held at 0 V
DC
.
Table 3. DC Electrical Specifications
Parameter
V
DD
Power Supply Voltage
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3V)
Control Voltage High
Control Voltage Low
0.7xV
DD
0.3xV
DD
Min
2.7
Typ
3.0
250
Max
3.3
500
Units
V
nA
V
V
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 8
Document No. 70-0069-04
│
UltraCMOS™ RFIC Solutions
PE4235
Product Specification
Typical Performance Data @ -40 °C to 85 °C (Unless Otherwise Noted)
Figure 4. Insertion Loss - RFC to RF1
Figure 5. Input 1dB Compression Point and IIP3
0
IIP3
-0.25
-40 C
40
-40 C
40
1dB Compression Point (dBm)
25 C
Insertion Loss (dB)
-0.5
25 C
85 C
IIP3 (dBm)
30
85 C
20
30
-0.75
20
-1
10
25 C
-40 C
1dB Compression
10
-1.25
-1.5
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
2000
2500
3000
3500
0
4000
Frequency (MHz)
Frequency (MHz)
Figure 6. Insertion Loss - RFC to RF2
Figure 7. Isolation - RFC to RF1
T = 25 °C
0
-40
8C
0
-0.25
-20
Insertion Loss (dB)
-0.5
25
8C
85
8C
Isolation (dB)
-40
-0.75
-1
-60
-1.25
-80
-1.5
0
500
1000
1500
2000
2500
3000
3500
4000
-100
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency (MHz)
Frequency (MHz)
Document No. 70-0069-04
│
www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 8
PE4235
Product Specification
Typical Performance Data @ 25 °C
Figure 8. Isolation – RFC to RF2
Figure 9. Isolation – RF1 to RF2, RF2 to RF1
0
0
-20
-20
RF2
Isolation (dB)
-60
Isolation (dB)
-40
-40
-60
RF1
-80
-80
-100
0
500
1000
1500
2000
2500
3000
3500
4000
-100
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency (MHz)
Frequency (MHz)
Figure 10. Return Loss – RFC
Figure 11. Return Loss – RF1, RF2
0
0
-10
Return Loss (dB)
Return Loss (dB)
-10
RF2
-20
-20
RF1
-30
-30
-40
0
500
1000
1500
2000
2500
3000
3500
4000
-40
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency (MHz)
Frequency (MHz)
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 8
Document No. 70-0069-04
│
UltraCMOS™ RFIC Solutions
PE4235
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4235 SPDT switch. The RF common port is
connected through a 50
Ω
transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50
Ω
transmission lines to the top
two SMA connectors on the right side of the board,
J2 and J3. A through transmission line connects
SMA connectors J4 and J5. This transmission line
can be used to estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a
coplanar waveguide with ground plane model using
a trace width of 0.0476”, trace gaps of 0.030”,
dielectric thickness of 0.028”, metal thickness of
0.0021” and
ε
r
of 4.4.
J6 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left pin,
the second pin to the right (J6-3) is connected to the
device CTRL input. The fourth pin to the right (J6-7)
is connected to the device V
DD
input. A decoupling
capacitor (100 pF) is provided on both CTRL and
V
DD
traces. It is the responsibility of the customer to
determine proper supply decoupling for their design
application. Removing these components from the
evaluation board has not been shown to degrade RF
performance.
Figure 12. Evaluation Board Layouts
Peregrine Specification 101/0085
Figure 13. Evaluation Board Schematic
Peregrine Specification 102/0108
Document No. 70-0069-04
│
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©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 8
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