MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.1
DESCRIPTION
The 7640 group, an enhanced family of CMOS 8-bit
microcontrollers, offers high-speed operation, large
internal-memory options, and a wide variety of stan-
dard peripherals. The series is code compatible with
the 38000, 7200, 7400, and the 7500 series, and pro-
vides many performance enhancements to the
instruction set.
This device is a single chip PC peripheral microcon-
troller based on the Universal Serial Bus (USB)
Version 1.1 specification. This device provides data
exchange between a USB-equipped host computer
and PC peripherals such as telephones, audio sys-
tems and digital cameras. See Figure 1.1 for a pin
layout diagram. See Figure 1.2 for the functional
block diagram.
1.2
MCU FEATURES
• Memory size
ROM .................................................. 32KB on chip
RAM ................................................... 1 KB on chip
• Programmable I/O ports ...................................... 66
.................................................... 8 bit X 7, 5 bit X 2
• Master Bus Interface (MBI) ....................... 17 signals
............................................................. 8 data lines
• Serial I/O ............................. 8 bit clock synchronous
• USB Function Control .............. 4 endpoints,1 control
• Interrupts ................................ 4 external, 19 internal
................................................ 1 software,1 system
• DMAC .......................... 2 channels, 16 address lines
(Max. 6M byte/sec. transfer speed in burst mode)
• Timers ......................................... 8 bit X 3, 16 bit X 2
• Number of Full duplex UARTs available ................... 2
• Supply voltage ............................. V
cc
= 4.15~5.25V
• Operating temperature range ................... -20 to 85°C
• Power-saving modes ..... WIT (Idle), STP (Clocks halt)
• Number of basic instructions ................................ 71
• Minimum instruction execution time ................. 83ns
(1-cycle instruction
................................... F
= 12 MHz)
•Clock frequency maximum .................. f(X
in
) = 24 MHz
........................................................ f(XC
in
) = 5 MHz
............................................................
F
= 12 MHz
1.3
APPLICATIONS
Cameras, games, musical instruments, modems
scanners, and PC peripherals.
P1
2
/AB10
P1
4
/AB12
P1
3
/AB11
P1
5
/AB13
P1
6
/AB14
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P7
4
/OBF
1
P7
3
/IBF
1
/HLDA
P7
2
/S1
P7
1
/(HOLD)
P7
0
/(SOF)
USB D+
USB D-
Ext. Cap
V
ss
V
cc
P6
7
/DQ7
P6
6
/DQ6
P6
5
/DQ5
P6
4
/DQ4
P6
3
/DQ3
P6
2
/DQ2
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24
40
39
38
37
36
35
P3
0
/RDY
P3
1
P3
2
P3
3
/DMA
out
P3
4
/Φ
out
P3
5
/SYNC
out
P3
6
/WR
P3
7
/RD
P8
0
/UTXD2/SRDY
P8
1
/URXD2/SCLK
P8
2
/CTS2/SRXD
P8
3
/RTS2/STXD
P8
4
/UTXD1
P8
5
/URXD1
P8
6
/CTS1
P8
7
/RTS1
M37640E8FP
M37640M8-XXXFP
P1
7
/AB15
34
33
32
31
30
29
28
27
26
25
P2
0
/DB0
P2
2
/DB2
P2
4
/DB4
P2
6
/DB6
P0
0
/AB0
P0
2
/AB2
P0
4
/AB4
P0
6
/AB6
P2
1
/DB1
P2
3
/DB3
P2
5
/DB5
P2
7
/DB7
P0
1
/AB1
P0
3
/AB3
P0
5
/AB5
P0
7
/AB7
P1
0
/AB8
AV
cc
CNVss/Vpp
X
out
V
cc
X
in
RESET
LPF
P1
1
/AB9
P6
1
/DQ1
P6
0
/DQ0
AV
ss
P4
4
/CNTR1
P4
3
/CNTR0
P5
0
/XC
in
P4
2
/INT1
P5
1
/T
out
/XC
out
P5
7
/W(R/W)
P5
2
/OBF
0
P4
1
/INT0
P5
6
/R(E)
P5
5
/A
0
P5
4
/S
0
P5
3
/IBF
0
V
ss
Package outline: 80P6N-A
Fig. 1.1. Pin Layout
P4
0
/EDMA
_
1
2
Ver 1.4
RESET
V
CC
V
CC
EDMA
24
68
33
35
66
34
40
X
IN
AVcc
V
SS
RD
WR SYNCout
RDY
HLDA HOLD
13
73
9
72
X
OUT
V
SS
Ext.Cap CNV
SS
19
10
16
17
74
X
CIN
X
COUT
LPF AV
SS
14
15
36
12
11
18
Frequency Synthesizer
CPU
A
Timer X (16)
Timer Y (16)
Fig. 1.2. Functional Block Diagram
RAM
X
Y
S
PC
H
PC
L
PS
Timer 3 (8)
Timer 1 (8)
Timer 2 (8)
1.4 FUNCTIONAL BLOCK DIAGRAM
ROM
Key-on Wake-up
T
OUT
CNTR
1
,CNTR
0
DMA
MBI
T
OUT
SOF
DQ (0-7)
INT
1
,
INT
0
DMA
OUT
USB
UART1(8)
UART2(8)
SIO (8)
S
1
,IBF
1
OBF
1
X
CIN
W(R/W)
R(E),A
0
S
0
,IBF
0
OBF
0
P8(8)
P6(8)
P5(8)
P4(5)
P7(5)
P3(8)
P2(8)
P1(8)
P0(8)
25 26 27 28 29 30 31 32
75 76 77 78 79 80 1
3
4
5
6
7
2
6 5 6 6 6 7 68 6 9
70 71
8 11 12
20 21 22 23 24
33 34 35 36 37 38 39 40
57 58 59 60 61 62 63 64
41 42 43 44 45 46 47 48
49 50 51 52 53 54 55 56
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7640 Group
P8
P5
P7
D+ D-
P6
P4
P3
P2
P1
P0
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.5 PIN DESCRIPTION AND LAYOUT
Table 1.1. Pin Description and Layout
NAME
P0
0
/AB0~ P1
7
/AB15
P2
0
/DB0 ~ P2
7
/DB7
I/O
I/O
I/O
DESCRIPTION
CMOS I/O port (address bus). When the MCU is in memory expansion or
microprocessor mode, these pins function as the address bus.
CMOS I/O port (data bus). When the MCU is in memory expansion or microprocessor
mode, these pins function as the data bus. These pins may also be used to implement
the Key-on Wake up function.
CMOS I/O port (Ready). When the MCU is in memory expansion or microprocessor
mode, this pin functions as RDY (hardware wait cycle control).
CMOS I/O port.
CMOS I/O port.
CMOS I/O port (DMAout). When the MCU is in memory expansion or microprocessor
mode, this pin is set to a “1” during a DMA transfer.
CMOS I/O port . When the MCU is in memory expansion or microprocessor mode,
this pin becomes
Φ
out pin.
CMOS I/O port (SYNCout). When the MCU is in memory expansion or
microprocessor mode, this pin becomes the SYNCout pin.
CMOS I/O port. (WR output). When the MCU is in memory expansion or microprocessor
mode, this pin becomes WR.
CMOS I/O port. (RD output). When the MCU is in memory expansion or microprocessor
mode, this pin becomes RD.
CMOS I/O port (EDMA: Expanded Data Memory Access). When the MCU is in memory
expansion or microprocessor mode, this pin can become the EDMA pin.
CMOS I/O port or external interrupt ports INT0 and INT1. These external interrupts can
be configured to be active high or low.
CMOS I/O port or Timer X input pin for pulse width measurement mode and event
counter mode or Timer X output pin for pulse output mode. This pin can also be used as
an external interrupt when Timer X is not in output mode. The interrupt polarity is
selected in the Timer X mode register.
PIN #
56-41
64-57
40
39
38
37
36
35
P3
0
/RDY
P3
1
P3
2
P3
3
/DMAout
I/O
I/O
I/O
I/O
P3
4
/Φout
P3
5
/SYNCout
I/O
I/O
P3
6
/WR
P3
7
/RD
P4
0
/EDMA
P4
1
/INT0~ P4
2
/INT1
I/O
I/O
I/O
I/O
I/O
34
33
24
23-22
P4
3
/CNTR0
21
P4
4
/CNTR1
I/O
CMOS I/O port or Timer Y input pin for pulse period measurement mode, pulse H-L
measurement mode and event counter mode or Timer Y output pin for pulse output
mode. This pin can also be used as an external interrupt when Timer Y is not in output
mode. The interrupt polarity is selected in the Timer Y mode register.
CMOS I/O port or XCin.
CMOS I/O port or Timer half pulse output pin (can be configured initially high or initially
low), or XCout.
CMOS I/O port or OBF
0
output to master CPU for data bus buffer 0.
CMOS I/O port or IBF
0
output to master CPU for data bus buffer 0.
CMOS I/O port or S
0
input from master CPU for data bus buffer 0.
CMOS I/O port or A
0
input from master CPU.
CMOS I/O port or R(E) input from master CPU.
CMOS I/O port or W(R/W) input from master CPU.
CMOS I/O port or master CPU data bus.
USB D- voltage line interface, a series resistor of 33
Ω
should be connected to this pin.
USB D+ voltage line interface, a series resistor of 33
Ω
should be connected to this pin.
CMOS I/O port or USB start of frame pulse output, an 80 ns pulse outputs on this pin for
every USB frame.
CMOS I/O port or HOLD pin.
CMOS I/O port or S
1
input from master CPU for data bus buffer 1.
20
P5
0
/XCin
P5
1
/Tout/XCout
P5
2
/OBF
0
P5
3
/IBF
0
P5
4
/S
0
P5
5
/A
0
P5
6
/R(E)
P5
7
/W(R/W)
P6
0
/DQ0~ P6
7
/DQ7
USB D-
USB D+
P7
0
/SOF
P7
1
/HOLD
P7
2
/S
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
12
11
8
7
6
5
4
3
2-1,
80-75
71
70
69
68
67
3
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NAME
I/O
DESCRIPTION
CMOS I/O port or IBF
1
output to master CPU for data bus buffer 1, or HLDA pin.
IBF
1
and HLDA are mutually exclusive. IBF
1
has priority over HLDA
CMOS I/O port or OBF
1
output to master CPU for data bus buffer 1.
CMOS I/O port or UART2 pin UTXD2 or SIO pin SRDY. UART2 and SIO are
mutually exclusive, UART2 has priority over SIO.
CMOS I/O port or UART2 pin URXD2 or SIO pin SCLK. UART2 and SIO are
mutually exclusive, UART2 has priority over SIO.
CMOS I/O port or UART2 pin CTS2 or SIO pin SRXD. UART2 and SIO are
mutually exclusive, UART2 has priority over SIO.
CMOS I/O port or UART2 pin RTS2 or SIO pin STXD. UART2 and SIO are
mutually exclusive, UART2 has priority over SIO.
CMOS I/O port or UART1 pin UTXD1.
CMOS I/O port or UART1 pin URXD1.
CMOS I/O port or UART1 pin CTS1.
CMOS I/O port or UART1 pin RTS1.
Power supply inputs for analog circuitry AVcc = 4.15~ 5.25V, AVss = 0V
Controls the processor mode of the chip. Normally connected to Vss or Vcc.
When the MCU is in EPROM program mode, this pin supplies the programming
voltage to the EPROM.
Power supply inputs: Vcc = 4.15~ 5.25V, Vss = 0V
To enter the reset state, this pin must be kept 'L' for more that 2 (20
Φ
cycles
µs
PIN #
P7
3
/IBF
1
/HLDA
P7
4
/OBF
1
P8
0
/UTXD2/SRDY
P8
1
/URXD2/SCLK
P8
2
/CTS2/SRXD
P8
3
/RTS2/STXD
P8
4
/UTXD1
P8
5
/URXD1
P8
6
/CTS1
P8
7
/RTS1
AVcc, AVss
CNVss/Vpp
Vcc,Vss
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
66
65
32
31
30
29
28
27
26
25
17,19
9
16/74
13/73
10
12
11
I
RESET
XCin
XCout
I
I
O
under normal Vcc conditions). If the crystal or ceramic resonator requires more
time to stabilize, extend this 'L' level time appropriately.
An external ceramic or quartz crystal oscillator can be connected between the
XCin and XCout pins. If an external clock source is used, connect the clock
source to the XCin pin and leave the XCout pin open.
Input and output signals to and from the internal clock generation circuit.
Connect a ceramic resonator or quartz crystal between Xin and Xout pins to set
the oscillation frequency. If an external clock is used, connect the clock source
to the Xin pin and leave the Xout pin open.
Loop filter for the frequency synthesizer.
An external capacitor (Ext. Cap) pin. When the USB transceiver voltage
converter is used, a 2µf or larger capacitor should connect between this pin and
Vss to ensure proper operation of the USB line driver. The voltage converter is
enabled by setting bit 4 of the USB control register (0013
16
) to a “1”.
Xin
Xout
LPF
Ext. Cap
I
O
O
I
14
15
18
72
4
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.6 PART NUMBERING
M37
640
M 8 -XXX FP
Package Type:
ROM Number
ROM capacity:
Memory type:
32 Kbytes
M: Mask ROM Version
E: EPROM version
One-time PROM version
FP: 80P6N
FS: 80D0
7640 Group
7600 Series
Fig. 1.3. Type no., memory size, and package
1.7 ROM EXPANSION
Table 1.2. ROM Expansion
ROM
Size (Bytes)
32K
M37640M8-XXXFP
M37640E8FP
One-time PROM version
M37640E8FS
Mask ROM version
EPROM version
1.8 CURRENTLY SUPPORTED PRODUCTS
Table 1.3. Currently Supported Products
Type No.
M37640M8-XXXFP
M37640E8FP
M37640E8FS
ROM
RAM
capacity capacity
32K bytes 1 K bytes
32K bytes 1 K bytes
32K bytes 1 K bytes
Package
type
80P6N-A
80P6N-A
80D0
Remarks
Mask ROM version
One-time PROM version
EPROM version
5
微控制器 MCU
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