HMA510/883
April 1997
16 x 16-Bit CMOS Parallel
Multiplier Accumulator
Description
The HMA510/883 is a high speed, low power CMOS 16 x
16-bit parallel multiplier accumulator capable of operating at
55ns clocked multiply-accumulate cycles. The 16-bit X and Y
operands may be specified as either two’s complement or
unsigned magnitude format. Additional inputs are provided
for the accumulator functions which include: loading the
accumulator with the current product, adding or subtracting
the accumulator contents and the current product, and pre-
loading the Accumulator Registers from the external inputs.
All inputs and outputs are registered. The registers are all
positive edge triggered, and are latched on the rising edge of
the associated clock signal. The 35-bit Accumulator Output
Register is broken into three parts. The 16-bit least signifi-
cant product (LSP), the 16-bit most significant product
(MSP), and the 3-bit extended product (XTP) Registers. The
XTP and MSP Registers have dedicated output ports, while
the LSP Register shares the Y-inputs in a multiplexed fash-
ion. The entire 35-bit Accumulator Output Register may be
preloaded at any time through the use of the bidirectional
output ports and the preloaded control.
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 16 x 16-Bit Parallel Multiplication with Accumulation
to a 35-Bit Result
• High-Speed (55ns) Multiply Accumulate Time
• Low Power CMOS Operation
- I
CCSB
= 500µA Maximum
- I
CCOP
= 7.0mA Maximum at 1.0MHz
• HMA510/883 is Compatible with the CY7C510 and the
IDT7210
• Supports Two’s Complement or Unsigned Magnitude
Operations
• Three-State Outputs
Ordering Information
PART NUMBER
HMA510GM-55/883
HMA510GM-65/883
HMA510GM-75/883
TEMP.
RANGE (
o
C)
-55 to 125
-55 to 125
-55 to 125
PACKAGE
68 Ld CPGA
68 Ld CPGA
68 Ld CPGA
PKG.
NO.
G68.B
G68.B
G68.B
Block Diagram
X0-15
16
RND
TC
SUB
Y0-15 P0-15
16
ACC
REGISTER
CLKY
CLKX
REGISTER
REGISTER
MULTIPLIER ARRAY
35
PRELOAD
CLKP
ACCUMULATOR
XTP REGISTER
MSP REGISTER
3
LSP REGISTER
16
35
16
OEX
OEM
OEL
P32-34
P16-31
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
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Copyright
©
Intersil Corporation 1999
File Number
2807.2
3-10
HMA510/883
Pinout
68 LEAD CPGA
TOP VIEW
11
N/C
X15
RND
ACC
CLKY
TC
PREL
CLKP
P33
10
X13
X14
OEL
SUB
CLKX
V
CC
OEX
OEM
P34
P32
N/C
9
X11
X12
P30
P31
8
X9
X10
P28
P29
7
X7
X8
TOP VIEW
P26
P27
6
X5
X6
P24
P25
5
X3
X4
P22
P23
4
X1
X2
P20
P21
3
Y0/P0
X0
Y10/
P10
Y11/
P11
G
Y12/
P12
Y13/
P13
H
Y14/
P14
Y15/
P15
J
P18
P19
2
N/C
Y1/P1
Y3/P3 Y5/P5
Y7/P7 Y8/P8
P16
P17
1
A
Y2/P2
B
Y4/P4 Y6/P6
C
D
GND
E
Y9/P9
F
N/C
K
L
Pin Descriptions
NAME
V
CC
GND
X0-X15
I
TYPE
DESCRIPTION
The +5V power supply pins. 0.1µF capacitors between the V
CC
and GND pins are recommended.
The device ground.
X-Input Data. These 16 data inputs provide the multiplicand which may be in two's complement or
unsigned magnitude format.
Y-Input/LSP Output Data. This 16-bit port is used to provide the multiplier which may be in two's com-
plement or unsigned magnitude format. It may also be used for output of the least significant product
(P0-P15) or for preloading the LSP Register.
MSP Output Data. This 16-bit port is used to provide the most significant product output (P16-P31).
It may also be used to preload the MSP Register.
XTP Output Data. This 3-bit port is used to provide the extended product output (P32-P34). It may
also be used to preload the XTP Register.
Two's Complement Control. Input data is interpreted as two's complement when this control is HIGH.
A LOW indicates the data is to be interpreted as unsigned magnitude format. This control is latched
on the rising edge of CLKX or CLKY.
Accumulate Control. When this control is HIGH, the Accumulator Output Register contents are added
to or subtracted from the current product, and the result is stored back into the Accumulator Output
Register.
When LOW, the product is loaded into the Accumulator Output Register overwriting the current con-
tents. This control is also latched on the rising edge of CLKX or CLKY.
Y0-Y15/P0-P15
I/O
P16-P3
I/O
P32-P34
I/O
TC
I
ACC
I
3-11
HMA510/883
Pin Descriptions
NAME
SUB
(Continued)
DESCRIPTION
Subtract Control. When both SUB and ACC are HIGH, the Accumulator Register contents are sub-
tracted from the current product. When ACC is HIGH and SUB is LOW, the Accumulator Register
contents and the current product are summed. The SUB control input is latched on the rising edge of
CLKX or CLKY.
Round Control. When this control is HIGH, a one is added to the most significant bit of the LSP. When
LOW, the product is unchanged.
Preload Control. When this control is HIGH, the three bidirectional ports may be used to preload the
Accumulator Registers. The three-state controls (OEX, OEM, OEL) must be HIGH, and the data will
be preloaded on the rising edge of CLKP. When this control is LOW, the Accumulator Registers func-
tion in a normal manner.
Y-Input/LSP Output Port Three-State Control. When OEL is HIGH, the output drivers are in the high
impedance state. This state is required for Y-data input or preloading the LSP Register. When OEL
is LOW, the port is enabled for LSP output.
MSP Output Port Three-State Control. A LOW on this control line enables the port for output. When
OEM is HIGH, the output drivers are in the high impedance state.
This control must be HIGH for preloading the MSP Register.
XTP Output Port Three-State Control. A LOW on this control line enables the port for output. When
OEX is HIGH, the output drivers are in the high impedance state. This control must be HIGH for pre-
loading the XTP Register.
X-Register Clock. The rising edge of this clock latches the X-Data Input Register along with the TC,
ACC, SUB and RND inputs.
Y-Register Clock. The rising edge of this clock latches the Y-Data Input Register along with the TC,
ACC, SUB and RND inputs.
Product Register Clock. The rising edge of CLKP latches the LSP, MSP and XTP Registers. If the
preload control is active, the data on the I/O ports is loaded into these registers. If preload is not ac-
tive, the accumulated product is loaded into the registers.
TYPE
I
RND
I
PREL
I
OEL
I
OEM
I
OEX
I
CLKX
I
CLKY
I
CLKP
I
3-12
HMA510/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input or Output Voltage Applied . . . . . . . . G ND -0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
θ
JA (
o
C/W)
θ
JC (
o
C/W)
Thermal Resistance (Typical, Note 1)
CPGA Package . . . . . . . . . . . . . . . . . .
43
10
Maximum Package Power Dissipation at 125
o
C
CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.17W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Storage Temperature Range . . . . . . . . . . 65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . 55
o
C to 125
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4800 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
TABLE 1. HMA5lO/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
GROUP A
SUBGROUPS
1, 2, 3
TEMPERATURE (
o
C)
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
PARAMETER
Logical One Input
Voltage
Logical Zero Input
Voltage
Output HIGH Voltage
SYMBOL
V
lH
V
IL
V
OH
V
OL
I
I
I
O
I
CCSB
TEST CONDITIONS
V
CC
= 5.5V
V
CC
= 4.5V
I
OH
= -400µA
V
CC
= 4.5V (Note 2)
I
OL
= +4.0mA
V
CC
= 4.5V (Note 2)
V
lN
= V
CC
or GND
V
OUT
= V
CC
or GND,
V
CC
= 5.5V
V
IN
= V
CC
or GND,
V
CC
= 5.5V,
Outputs Open
f = 1.0MHz, V
IN
= V
CC
or GND V
CC
= 5.5V
(Note 3)
(Note 4)
MIN
2.2
MAX
-
UNITS
V
1, 2, 3
-
0.8
V
1, 2, 3
2.6
-
V
Output LOW Voltage
1, 2, 3
-
0.4
V
µA
µA
µA
Input Leakage Current
Output or I/O Leakage
Current
Standby Power Supply
Current
1, 2, 3
1, 2, 3
-10
-10
+10
+10
1, 2, 3
-
500
Operating Power Supply
Current
I
CCOP
1, 2, 3
-55
≤
T
A
≤
125
-
7.0
mA
Functional Test
NOTES:
FT
7, 8
-55
≤
T
A
≤
125
-
-
2. Interchanging of force and sense conditions is permitted.
3. Operating Supply Current a proportional to frequency, typical rating is 5mA/MHz.
4. Tested as follows: f = 1MHz, V
IH
(clock inputs) = 3.2V, V
lH
(all other inputs) = 2.6V, V
IL
= 0.4V, V
OH
≥
1.5V, and V
OL
≤
1.5V.
TABLE 2. HMA510/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
-55
PARAMETER
Multiply Accumu-
late Time
Input Setup Time
SYMBOL
t
MA
t
S
(NOTE 5)
CONDITIONS
GROUP A
SUBGROUPS
9, 10, 11
TEMPERATURE (
o
C)
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-65
-75
MIN MAX MIN MAX MIN MAX UNITS
-
55
-
65
-
75
ns
9, 10, 11
20
-
25
-
25
-
ns
3-13
HMA510/883
TABLE 2. HMA510/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested
-55
PARAMETER
Clock HIGH
Pulse Width
Clock LOW
Pulse Width
Output Delay
Three-State
Enable Time
NOTES:
5. AC Testing as follows: V
CC
= 4.5V and 5.5V. Input levels 0V and 3.0V (0V and 3.2V tor clock inputs). Timing reference levels = 1.5V,
Output load per test load circuit, with V
1
= 2.4V, R
1
= 500Ω and C
L
= 40pF.
6. Transition is measured at 1200mV from steady state voltage, Output loading per test load circuit, with V
1
= 1.5V, R
1
= 500Ω and C
L
=
40pF.
TABLE 3. HMA510/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
-55
PARAMETER
lnput Capacitance
SYMBOL
C
IN
TEST
CONDITIONS
V
CC
= Open,
f = 1MHz All mea-
surements are ref-
erenced to device
GND
NOTE
1
TEMPERATURE (
o
C)
T
A
= 25
-65
-75
SYMBOL
t
PWH
t
PWL
t
D
t
ENA
(Note 5)
(NOTE 5)
CONDITIONS
GROUP A
SUBGROUPS
9, 10, 11
TEMPERATURE (
o
C)
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-65
-75
MIN MAX MIN MAX MIN MAX UNITS
20
-
25
-
25
-
ns
9, 10, 11
20
-
25
-
25
-
ns
9, 10, 11
9, 10, 11
-
-
30
30
-
-
35
30
-
-
35
35
ns
ns
MIN MAX MIN MAX MIN MAX UNITS
-
10
-
10
-
10
pF
Output Capacitance
I/O Capacitance
Input Hold Time
Three-State Disable
Time
Output Rise Time
Output Fall Time
NOTE:
C
OUT
C
I/O
t
H
t
DIS
t
r
t
f
From 0.8V to 2.0V
From 2.0V to 0.8V
1
1
1
1
T
A
= 25
T
A
= 25
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-
-
3
-
10
15
-
30
-
-
3
-
10
15
-
30
-
-
3
-
10
15
-
30
pF
pF
ns
ns
1
1
-
-
10
10
-
-
10
10
-
-
10
10
ns
ns
7. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design and after major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
Interim Test
PDA
Final Test
Group A
Groups C and D
METHOD
100%/5004
100%/5004
100%
100%
-
Samples/5005
SUBGROUPS
-
-
1
2, 3, 8A, 8B, 10,11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
3-14
FPGA/CPLD
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