PRELIMINARY
HM6C5332
HM6C5332 – 1.2GHz/250MHz Dual Frequency Synthesizer
Features
Description
The HM6C5332 of full CMOS monolithic, dual frequency
synthesizer is to be used as a local oscillator for RF and IF
of a dual conversion transceiver. It is fabricated using
Hyundai’s standard CMOS process.
HM6C5332 contains dual modulus prescalers. A 64/65 or
a 128/129 prescaler can be selected for RF synthesizer
and a 8/9 or 16/17 prescaler can be selected for IF
synthesizer. Using digital phase locked loop technique,
HM6C5332 provides the tuning voltage for voltage
controlled oscillators to generate very stable low noise RF
& IF local oscillator signals. Serial data is transferred into
the HM6C5332 via three wire interface (Data, Enable,
Clock). Supply voltage can range from 2.7 to 3.6 V.
HM6C5332 features very low current consumption; 3.2mA
at 3.0V.
HM6C5332 is available in a 20-pin TSSOP package and
24-pin LGA (Leadless Grid Array) package
Applications
Functional Block Diagram
Portable Wireless Communications
Cordless and Cellular Telephone Systems
Wireless Local Area Networks(WLANs)
Cable TV Tuners(CATV)
Other Wireless Communication Systems
#$%
Full CMOS RF frequency synthesizer
Low Current Consumption
Selectable Powersave Mode
Dual Modulus Prescaler
Selectable Charge Pump High Z State
2.7V to 3.6V Operation
Small Out Line 20 Pin TSSOP Package
24 Pin LGA(Leadless Grid Array) Package
f
IN
IF
D
O
IF
D
O
RF
!"
f
IN
RF
PRELIMINARY
Pin Assignment
Leadless Grid Array Package
Thin Shrink Small Outline Package ™
Pin Description
Pin No.
HM6C5332
24-pin LGA
Package
Pin No.
HM6C5332
20-pin TSSOP
Package
PIN
NAME
I/O
Description
24
1
VDDRF
-
Power supply voltage input for RF analog and RF digital circuits. Input may
range from 2.7V to 3.6V. VDDRF must equal VDDIF. Bypass capacitors
should be placed as close as possible to this pin and be connected directly
to the ground plane.
Power Supply for RF charge pump. Must be
≥
VDDRF.
Internal RF charge pump output. For connection to a loop filter for driving
the input of an external VCO.
Ground for RF digital circuitry.
RF prescaler input. Small signal input from the VCO.
This pin is to provide a bypass capacitor to the internal voltage supply and
bypass capacitor must be placed between this pin and RF analog GND(Pin
7). With a slight performance degradation, this pin may be NC.
Ground for RF analog circuitry.
Oscillator input. The input has a VDDRF/2 input threshold and can be
driven from an external CMOS or TTL logic gate.
Ground for data interface, FoLD, and oscillator circuits.
Multiplexed output of the RF/IF programmable or reference dividers, and
RF/IF lock detect signals. CMOS output(See
Programmable Modes)
High impedance CMOS Clock input. Data for the various counters is
clocked in on the rising edge, into the 22-bit shift register.
Binary serial data input. Data entered MSB first. The last two bits are the
control bits. High impedance CMOS input.
Load enable high impedance CMOS input. When LE goes HIGH, data
stored in the shift register is loaded into one of the 4 appropriate
latches(control bit dependent).
2
3
4
5
6
7
8
10
11
12
14
2
3
4
5
6
7
8
9
10
11
12
VPPRF
DoRF
VSRFD
finRF
VIRF
VSRFA
OSCin
VSS
FoLD
Clock
Data
-
O
-
I
-
-
I
-
O
I
I
15
13
LE
I
PRELIMINARY
Pin No.
HM6C5332
24-pin LGA
Package
16
17
Pin No.
HM6C5332
20-pin TSSOP
Package
14
15
PIN
NAME
VSIFA
VIIF
I/O
Description
-
-
18
19
20
22
23
16
17
18
19
20
finIF
VSIFD
DoIF
VPPIF
VDDIF
I
-
O
-
-
Ground for IF analog circuitry.
This pin is to provide a bypass capacitor to the internal voltage supply and
bypass capacitor must be placed between this pin and IF analog GND(Pin
14). With a slight performance degradation, this pin may be NC.
IF prescaler input. Small signal input from the VCO.
Ground for IF digital circuitry.
Internal IF charge pump output. For connection to a loop filter for driving
the input of an external VCO.
Power Supply for IF charge pump. Must be
≥
VDDIF.
Power supply voltage input for IF analog, IF digital, data interface, FoLD,
and oscillator circuits. Input may range from 2.7V to 3.6V. VDDIF must
equal VDDRF. Bypass capacitors should be placed as close as possible to
this pin and be connected directly to the ground plane.
No Connect
1,9,13,21
X
NC
-
Block Diagram
FoLD
%
" (*
+,+
+,+
DoRF
(
%
&
'
)
%
&
'
)
(
DoIF
finRF
!)
)
'
finIF
)
!
)
!"#
#
LE
OSCin
!
Data
Clock
!
!"#
PRELIMINARY
Absolute Maximum Ratings
Power Supply Voltage
VDD
VPP
Voltage on Any Pin
with GND = 0V (V
I
)
Storage Temperature Range (T
S
)
Lead Temperature (solder 4 sec.) (T
L
)
Thermal Resistance(Typical)
θ
JA
(°C/W)
TSSOP Package
130°C
-0.3V to +4.2V
-0.3V to +4.2V
-0.3V to +4.2V
-65°C to +150°C
260°C
Operating Conditions
Power Supply Voltage
VDD
VPP
Operating Temperature(T
A
)
2.7V to 3.6V
VDD to 3.6V
-40°C to 85°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Other conditions
above those indicated in the operational sections of this specification are not implied.
Electrical Characteristics
Symbol
Parameter
V
DD
= 3.0V, -40°C < T
A
< 85°C, Except as Specified
Conditions
RF
V
DD
=2.7V to 3.6V,
f
Φ
= 10KHz
V
DD
=2.7V to 3.6V,
f
Φ
= 10KHz
Min
Typ
2.2
Max
Units
mA
I
DD
I
DD-PWDN
f
IN
RF
f
IN
IF
f
OSC
f
Φ
Pf
IN
RF
Pf
IN
IF
V
OSC
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
V
OH
V
OL
t
CS
t
CH
t
CWH
t
CWL
t
ES
t
EW
Power Supply Current
IF
Powerdown Current
Operating Frequency
Operating Frequency
Oscillator Frequency.
Maximum Phase Detector Freq.
RF Input Sensitivity
IF Input Sensitivity
Oscillator Sensitivity
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Oscillator Input Current
Oscillator Input Current
High-Level Output Voltage
Low-Level Output Voltage
Data Clock Setup Time
Data Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
Clock to Load Enable Setup Time
Load Enable Pulse Width
4.1
1.0
1
0.5
50
4
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
1.2
250
40
-
0
0
-
-
0.2 V
DD
1.0
1.0
100
-
-
0.4
-
mA
µA
GHz
MHz
MHz
MHz
dBm
dBm
V
PP
V
V
µA
µA
µA
µA
V
V
DD
=3.0V
V
DD
=2.7V to 3.6V
V
DD
=2.7V to 3.6V
OSC
IN
*
*
V
IH
=V
DD
=3.6V*
V
IL
=0V, V
DD
=3.6V*
V
IH
=V
DD
=3.6V
V
IL
=0V, V
DD
=3.6V
I
OH
= -500
µA
I
OL
= 500
µA
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
-10
-10
0.5
0.8 V
DD
-
-1.0
-1.0
-
-100
V
DD
-0.4
-
50
10
50
50
50
50
V
ns
-
-
-
-
* Clock, Data and LE. Does not include f
IN
RF, f
IN
IF and OSC
IN
.
PRELIMINARY
Functional Description
The simplified block diagram below shows the 22-bit data
register, two 15-bit R Counters and the 15-bit and 18-bit N
Counters (intermediate latches are not shown). The data
stream is clocked (on the rising edge of Clock) into the
DATA input, MSB first. The last two bits are the Control
Bits. The DATA is transferred into the counters as follows:
CONTROL BITS
C1
C2
0
0
0
1
1
0
1
1
D
O
IF
DATA LOCATION
IF R Counter
RF R Counter
IF N Counter
RF N Counter
f
IN
IF
#$%
!"
D
O
RF
f
IN
RF
Programmable Reference Dividers (IF and RF R Counters)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22bit shift register into a latch which
sets the 15-bit R Counter. Serial data format is shown below.
15-Bit Programmable Reference Divider Ratio (R Counter)
DIVIDE
RATIO
3
4
•
R
15
0
0
•
R
14
0
0
•
R
13
0
0
•
R
12
0
0
•
R
11
0
0
•
R
10
0
0
•
R
9
0
0
•
R
8
0
0
•
R
7
0
0
•
R
6
0
0
•
R
5
0
0
•
R
4
0
0
•
R
3
0
1
•
R
2
1
0
•
R
1
1
0
•
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NOTES:
1. Divide ratios less than 3 are prohibited.
2. Divide ratio: 3 to 32767.
3. R1 to R15: These bits select the divide ratio of the programmable reference divider.
4. Data is shifted in MSB first.
stm32/stm8
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