CY28317-2
FTG for Mobile VIA™ PL133T and PLE133T Chipsets
1CY28317-2
Features
• Single-chip system frequency synthesizer for mobile
VIA PL133T and PLE133T chipsets
• Programmable clock output frequency with less than
1 MHz increment
• Integrated fail-safe Watchdog Timer for system
recovery
• Automatic switch to HW-selected or SW-programmed
clock frequency when Watchdog Timer time-out occurs
• System RESET generation capability after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte Read/Write and block Read/ Write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength for SDRAM and PCI
output clocks
• Programmable output skew for CPU, PCI and SDRAM
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Available in 48-pin SSOP and TSSOP packages
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
Block Diagram
VDD_REF
REF0
X1
X2
XTAL
OSC
PLL Ref Freq
Pin Configuration
[1]
GND_CPU
*FS2/REF1
REF0
VTT_PWRGD#
REF1/FS2*
MULT_SEL
IREF
VTT_PWRGD#
PCI_STOP#
CPU_STOP#
PD#
PLL 1
÷2,3,4
CPU0:1, CPUT, CPUC
VDD_PCI
PCI0_F/FS4*
PCI1/FS3*
PCI2:6
SDATA
SCLK
SMBus
Logic
Reset
Logic
PLL2
÷2
RST#
VDD_48MHz
48MHz/FS0*
VDD_REF
GND_REF
X1
X2
VDD_PCI
*FS4/PCI0_F
*FS3/PCI1
GND_PCI
PCI2
PCI3
PCI4
PCI5
PCI6
SDRAMIN
*CPU_STOP#
*PCI_STOP#
*PD#
*MULT_SEL
GND_48MHz
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CPU0
CPU1
VDD_CPU_2.5
VDD_CPU_3.3
CPUT
CPUC
GND_CPU
RST#
IREF
SDRAM6
GND_SDRAM
SDRAM0
SDRAM1
VDD_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
VDD_SDRAM
VDD_48MHz
48MHz/FS0*
24_48MHz/FS1*
SCLK
CY28317-2
SDRAMIN
7
24_48MHz/FS1*
VDD_SDRAM
SDRAM0:6
Note:
1. Signals marked with ‘*’ have internal pull-up resistors.
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 20
www.SpectraLinear.com
CY28317-2
Pin Definitions
Pin Name
CPU0, CPU1
CPUT, CPUC
PCI2:6
PCI1/FS3
Pin No.
48, 47
44, 43
13, 14, 15,
16, 17
11
Pin Type
O
O
O
I/O
Pin Description
CPU Clock Output 0 through 1:
CPU clocks for processor and chipset.
Differential CPU Clock Output:
Differential CPU clocks for processor.
PCI Clock Outputs 2 through 6:
3.3V 33-MHz PCI clock outputs. Frequency
is set by FS0:4 inputs or through serial data interface.
Fixed PCI Clock Output/Frequency Select 3:
3.3V PCI clock outputs. As an
output, the frequency is set by FS0:4 inputs or through serial data interface. This
pin also serves as a power-on strap option to determine device operating
frequency, as described in
Table 6.
Fixed PCI Clock Output/Frequency Select 4:
3.3V Free-running PCI clock
outputs. This pin also serves as a power-on strap option to determine device
operating frequency as described in
Table 6.
Reset# Output:
Open drain system reset output.
PCI0_F/FS4
10
I/O
RST#
41
O
(open-drai
n)
I/O
48MHz/FS0
27
48 MHz Output/Frequency Select 0:
3.3V 48-MHz non-spread spectrum
output. This pin also serves as a power-on strap option to determine device
operating frequency as described in
Table 6.
24_48MHz Output/Frequency Select 1:
3.3V 24 or 48 MHz non-spread
spectrum output. This pin also serves as a power-on strap option to determine
device operating frequency as described in
Table 6.
Reference Clock Output 1/Frequency Select 2:
3.3V 14.318 MHz output
clock. This pin also serves as a power-on strap option to determine device
operating frequency as described in
Table 6.
Reference Clock Output 0:
3.3V 14.318-MHz output clock.
SDRAM Buffer Input Pin:
Reference input for SDRAM buffer.
SDRAM Outputs:
These thirteen dedicated outputs provide copies of the signal
provided at the SDRAMIN input.
Clock pin for SMBus circuitry.
Data pin for SMBus circuitry.
Crystal Connection or External Reference Frequency Input:
This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection or
as an external reference frequency input.
Crystal Connection:
An output connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
Power Down Control:
LVTTL-compatible input that places the device in
power-down mode when held LOW.
CPU Output Control:
3.3V LVTTL compatible input that stops CPU0, CPU1,
CPUT, and CPUC when held LOW.
PCI Output Control:
3.3V LVTTL compatible input that stop PCI1:6 when held
LOW.
Current Reference Input:
Current reference for differential CPU output.
CPUT and CPUC Output Control:
Control the current multiplier for differential
CPU output. Set this pin LOW for 1.0V output swing and set this pin HIGH for
0.7V output swing.
VTT_PWRGD#:
3.3V LVTTL compatible input that controls the FS0:4 to be
latched and enables all outputs. CY28316 will sample the FS0:4 inputs and
enable all clock outputs after all the VDD become valid and VTT_PWRGD# is
held LOW.
24_48MHz/
FS1
REF1/FS2
26
I/O
2
I/O
REF0
SDRAMIN
SDRAM0:6
SCLK
SDATA
X1
3
18
37, 36, 34,
33, 31, 30, 39
25
24
7
O
I
O
I
I/O
I
X2
PD#
CPU_STOP#
PCI_STOP#
IREF
MULT_SEL
8
21
19
20
40
22
O
I
I
I
I
I
VTT_PWRGD#
4
I
Rev 1.0, November 25, 2006
Page 2 of 20
CY28317-2
Pin Definitions
(continued)
Pin Name
VDD_REF,
VDD_PCI,
VDD_SDRAM,
VDD_48MHz
VDD_CPU_3.3
VDD_CPU_2.5
GND_REF,
GND_PCI,
GND_SDRAM,
GND_48MHz,
GND_CPU
Pin No.
5, 9, 28, 29,
35, 45
Pin Type
P
Pin Description
Power Connection:
Power supply for core logic, PLL circuitry, SDRAM outputs,
PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output.
Connect to 3.3V supply.
46
1, 6, 12, 23,
32, 38, 42
P
G
Power Connection:
Power supply for CPU outputs. Connect to 2.5V supply.
Ground Connections:
Connect all ground pins to the common system ground
plane.
Table 1. Swing Select Functions
Mult0
0
1
Board Target
Trace/Term Z
60
50
Reference R, IREF=
VDD/(3*Rr)
Rr = 221 1%
IREF = 5.00 mA
Rr = 475 1%
IREF = 2.32 mA
Output Current
I
OH
= 4*IREF
I
OH
= 6*IREF
V
OH
@ Z
1.0V @ 50
0.7V @ 50
Rev 1.0, November 25, 2006
Page 3 of 20
CY28317-2
Serial Data Interface
The CY28317-2 features a two-pin, serial data interface that
can be used to configure internal register settings that control
particular device functions.
Data Protocol
The clock driver serial protocol supports byte/word Write,
byte/word Read, block Write and block Read operations from
Table 2. Command Code Definition
Bit
7
6:0
Descriptions
0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation
Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at ‘0000000’.
the controller. For block Write/Read operations, the bytes must
be accessed in sequential order from lowest to highest byte
with the ability to stop after any complete byte has been trans-
ferred. For byte/word Write and byte Read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code.
The definition for the command code is defined as shown in
Table 2.
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
...
...
...
...
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Byte count – 8 bits
Acknowledge from slave
Data byte 0 – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte N/Slave acknowledge...
Data byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
...
...
...
...
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave - 8 bits
Not acknowledge
Stop
Block Read Protocol
Description
Rev 1.0, November 25, 2006
Page 4 of 20
CY28317-2
Table 4. Word Read and Word Write Protocol
Word Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Data byte low – 8 bits
Acknowledge from slave
Data byte high – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Data byte low from slave – 8 bits
Acknowledge
Data byte high from slave – 8 bits
Not acknowledge
Stop
Word Read Protocol
Description
19
20:27
28
29:36
37
38
19
20
21:27
28
29
30:37
38
39:46
47
48
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Data byte from slave – 8 bits
Not acknowledge
Stop
Byte Read Protocol
Description
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Rev 1.0, November 25, 2006
Page 5 of 20
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