CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
DD
= V
AA
+ = V
REF
+ = 3.3V, V
SS
= V
AA
- = V
REF
- = GND, CLK = 600kHz (J suffix),
CLK = 500kHz (K suffix), Unless Otherwise Specified
25
o
C
-
40
o
C TO 85
o
C
MAX
MIN
MAX
UNITS
PARAMETER
ACCURACY
Resolution
Integral Linearity Error, INL
(End Point)
Differential Linearity Error, DNL
J
K
J
K
Gain Error, FSE
(Adjustable to Zero)
Offset Error, V
OS
(Adjustable to Zero)
DYNAMIC CHARACTERISTICS
Signal to Noise Ratio, SINAD
RMS Signal
RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
RMS Noise
Total Harmonic Distortion, THD
J
K
Spurious Free Dynamic Range,
SFDR
ANALOG INPUT
Input Current, Dynamic
Input Current, Static
J
K
J
K
J
K
J
K
J
K
TEST CONDITIONS
MIN
TYP
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±4.0
±2.5
±4.0
±2.0
±2.0
±2.0
±3.0
±2.5
12
-
-
-
-
-
-
-
-
-
±4.0
±2.5
±4.0
±2.0
±2.0
±2.0
±3.0
±2.5
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
f
S
= 600kHz, f
IN
= 1kHz
f
S
= 500kHz, f
IN
= 1kHz
f
S
= 600kHz, f
IN
= 1kHz
f
S
= 500kHz, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= 600kHz, f
IN
= 1kHz
f
S
= 500kHz, f
IN
= 1kHz
-
-
-
-
-
-
-
-
61.5
63.9
63.2
65.1
-68.4
-70.8
69.0
71.8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dBc
dBc
dB
dB
At V
IN
= V
REF
+, 0V
Conversion Stopped
-
-
±50
±0.4
±100
±10
-
-
±100
±10
µA
µA
6-1804
HI5813
Electrical Specifications
V
DD
= V
AA
+ = V
REF
+ = 3.3V, V
SS
= V
AA
- = V
REF
- = GND, CLK = 600kHz (J suffix),
CLK = 500kHz (K suffix), Unless Otherwise Specified
(Continued)
25
o
C
PARAMETER
Input Bandwidth -3dB
Reference Input Current
Input Series Resistance, R
S
Input Capacitance, C
SAMPLE
Input Capacitance, C
HOLD
DIGITAL INPUTS
OEL, OEM, STRT
High-Level Input Voltage, V
IH
Low-Level Input Voltage, V
IL
Input Leakage Current, I
IL
Input Capacitance, C
IN
DIGITAL OUTPUTS
High-Level Output Voltage, V
OH
Low-Level Output Voltage, V
OL
Three-State Leakage, I
OZ
Output Capacitance, C
OUT
TIMING
Conversion Time (t
CONV
+ t
ACQ
)
(Includes Acquisition Time)
Clock Frequency
Clock Pulse Width, t
LOW
, t
HIGH
Aperture Delay, t
D
APR
Clock to Data Ready Delay, t
D1
DRDY
Clock to Data Ready Delay, t
D2
DRDY
Start Removal Time, t
R
STRT
Start Setup Time, t
SU
STRT
Start Pulse Width, t
W
STRT
Start to Data Ready Delay, t
D3
DRDY
Output Enable Delay, t
EN
Output Disabled Delay, t
DIS
POWER SUPPLY CHARACTERISTICS
Supply Current, I
DD
+ I
AA
NOTE:
2. Parameter guaranteed by design or characterization, not production tested.
Logic analyzers are widely used tools in digital design verification and debugging. They can verify the proper functioning of digital circuits and help users identify and troubleshoot faults. They ...[详细]