HM62G18512 Series
8M Synchronous Fast Static RAM
(512k-word
×
18-bit)
ADE-203-1185 (Z)
Preliminary
Rev. 0.0
Jun. 12, 2000
Description
The HM62G18512 is a synchronous fast static RAM organized as 512-kword
×
18-bit. It has realized high
speed access time by employing the most advanced CMOS process and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-
bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
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Power supply: 3.3 V +10%, –5%
Clock frequency: 200 MHz to 250 MHz
Internal self-timed late write
Byte write control (2 byte write selects, one for each 9-bit)
Optional
×36
configuration
HSTL compatible I/O
Programmable impedance output drivers
User selective input trip-point
Differential, HSTL clock inputs
Asynchronous
G
output control
Asynchronous sleep mode
Limited set of boundary scan JTAG IEEE 1149.1 compatible
Protocol: Single clock register-register mode
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specifications.
HM62G18512 Series
Ordering Information
Type No.
HM62G18512BP-4
HM62G18512BP-5
Access time
2.1 ns
2.5 ns
Cycle time
4.0 ns
5.0 ns
Package
119-bump 1. 27 mm
14 mm
×
22 mm BGA (BP-119A)
Pin Arrangement
119-bumps BGA
1
A
2
3
4
NC
NC
5
6
7
VDDQ SA0 SA6
SA4 SA2 VDDQ
SA8 SA18 NC
NC
B
NC
NC
SA7
C
NC SA13 SA3 VDD SA5 SA1
D
DQb0 NC
VSS
ZQ
SS
G
VSS DQa4 NC
VSS
NC DQa5
E
NC DQb1 VSS
F
VDDQ NC
VSS
VSS DQa6 VDDQ
VSS
NC DQa7
G
H
NC DQb2
SWEb
NC
DQb3 NC
VSS
NC
VSS DQa8 NC
J
VDDQ VDD VREF VDD VREF VDD VDDQ
K
NC DQb8 VSS
K
K
VSS
NC DQa3
L
DQb7 NC
VSS
SWEa
DQa2 NC
NC VDDQ
M
N
VDDQ DQb6 VSS
SWE
VSS
DQb5 NC
VSS SA16 VSS DQa1 NC
NC DQa0
P
NC DQb4 VSS SA14 VSS
R
NC
SA9
M1
VDD
M2 SA10 NC
T
NC SA17 SA11 NC SA12 SA15 ZZ
U
VDDQ TMS TDI TCK TDO
NC VDDQ
(Top view)
2
HM62G18512 Series
Pin Description
Name
V
DD
V
SS
V
DDQ
V
REF
K
K
SS
SWE
SAn
SWEx
G
ZZ
ZQ
DQxn
M1, M2
TMS
TCK
TDI
TDO
NC
I/O type
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Input
Input
Input
Input
Output
—
Descriptions
Core power supply
Ground
Output power supply
Input reference: provides input reference voltage
Clock input. Active high.
Clock input. Active low.
Synchronous chip select
Synchronous write enable
Synchronous address input
Synchronous byte write enables
Asynchronous output enable
Power down mode select
Output impedance control
Synchronous data input/output
Output protocol mode select
Boundary scan test mode select
Boundary scan test clock
Boundary scan test data input
Boundary scan test data output
No connection
1
x = a, b
n = 0, 1, 2...8
n = 0, 1, 2...18
x = a, b
Notes
M1
V
SS
M2
V
DD
Protocol
Synchronous register to register operation
Notes
2
Notes: 1. ZQ is to be connected to V
SS
via a resistance RQ where 150
Ω ≤
RQ
≤
300
Ω,
if ZQ = V
DDQ
or
open, output buffer impedance will be maximum. A case of minimum impedance, it needs to
connect over 120
Ω
between ZQ and V
SS
.
2. There is 1 protocol with mode pin. Mode control pins (M1, M2) are to be tied either V
DD
or V
SS
respectively. The state of the Mode control inputs must be set before power-up and must not
change during device operation. Mode control inputs are not standard inputs and may not meet
V
IH
or V
IL
specification. This SRAM is tested only in the synchronous register to register
operation.
3
HM62G18512 Series
Block Diagram
19
A0 to A18
JTAG
register
R-Add
register
19
W-Add
register
MUX
Row decoder
19
Memory
cell array
(512k
×
18)
Column decoder
1
SS
JTAG
register
SWE
JTAG
register
2
SWEx
JTAG
register
G
SS
register
WRC
WA
SWE
register
Match
SWEx
register
2
SA
Multiplex
DOC
JTAG
register
CLK
control
JTAG
register
JTAG
register
D-in
register
D-out
register
K
K
OB
18
DQa0-8
DQb0-8
ZZ
V
REF
JTAG
register
ZQ
JTAG
register
TDI
TCK
TMS
Impedance
contorol logic
JTAG tap
controller
TDO
4
HM62G18512 Series
Operation Table
ZZ
H
L
L
L
L
L
L
SS
×
H
×
L
L
L
L
G
×
×
H
L
×
×
×
SWE
×
×
×
H
L
L
L
SWEa SWEb
K
×
×
×
×
L
L
H
×
×
×
×
L
H
L
×
L-H
×
L-H
L-H
L-H
L-H
K
×
H-L
×
H-L
H-L
H-L
H-L
Operation
sleep mode
Dead
(not selected)
Dead
(Dummy read)
Read
Write a, b byte
Write a byte
Write b byte
DQ (n)
High-Z
×
High-Z
×
High-Z
High-Z
High-Z
DQ (n + 1)
High-Z
High-Z
High-Z
Dout
(a,b)0-8
Din (a,b)0-8
Din (a)0-8
Din (b)0-8
Notes: 1.
×
means don’t care for synchronous inputs, and H or L for asynchronous inputs.
2.
SWE, SS, SWEa
to
SWEb,
SA are sampled at the rising edge of K clock.
3. Although differential clock operation is implied, this SRAM will operate properly with one clock
phase (either K or
K)
tied to V
REF
. Under such single-ended clock operation, all parameters
specified within this document will be met.
5
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