PRELIMINARY
CY37064V
UltraLogic
TM
3.3V 64-Macrocell ISR
TM
CLPD
Features
• 64 macrocells in four logic blocks
• 3.3V In-System Reprogrammable™ (ISR™)
— JTAG-compliant on-board programming
— Design changes don’t cause pinout changes
— Design changes don’t cause timing changes
• IEEE standard 3.3V operation
— 3.3V ISR
— 5V tolerant
• Up to 64 I/Os
— plus 5 dedicated inputs including 4 clock inputs
• High speed
— f
MAX
= 125 MHz
— t
PD
= 10 ns
— t
S
= 5.5 ns
•
•
•
•
•
•
•
•
•
— t
CO
= 6.5 ns
Product-term clocking
IEEE 1149.1 JTAG boundary scan
Programmable slew rate control on individual I/Os
Low power option on individual logic block basis
User-Programmable Bus Hold capabilities on all I/Os
Simple Timing Model
PCI compliant
[1]
44−100 pins in TQFP, PLCC and CLCC packages
Pinout compatible with the CY37064, CY37032/37032V,
CY37128/37128V
Logic Block Diagram (100-pin TQFP)
Input
Clock/
Input
1
4
4
36
I/O
0
−I/O
15
16 I/Os
LOGIC
BLOCK
A
LOGIC
BLOCK
B
16
36
16 I/Os
I/O
16
−I/O
31
16
36
16
4
LOGIC
BLOCK
D
LOGIC
BLOCK
C
16 I/Os
I/O
48
−I/O
63
PIM
36
16 I/Os
I/O
32
−I/O
47
16
TDI
TCLK
TMS
32
JTAG Tap
Controller
TDO
32
37064V-1
Selection Guide
CY37064V-143
Maximum Propagation Delay, t
PD
(ns)
Minimum Set-Up, t
S
(ns)
Maximum Clock to Output, t
CO
(ns)
Typical Supply Current, I
CC
(mA) in Low Power Mode
Note:
1. Due to the 5V tolerant nature of the I/Os, the I/Os are not clamped to V
CC
.
CY37064V-100
12
7.5
6.5
30
8.5
5.0
6.0
30
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA95134
•
408-943-2600
January 6, 1999
PRELIMINARY
Functional Description
The CY37064V is an In-System Reprogrammable (ISR) Com-
plex Programmable Logic Device (CPLD) and is part of the
Ultra37000™ family of high-density, high-speed CPLDs. Like
all members of the Ultra37000 family, the CY37064V is de-
signed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
# of
Pins
44
84
100
# Buried
Macrocells
32
0
0
# I/O
Macrocells
32
64
64
Package
Types
TQFP PLCC
,
PLCC
TQFP
CY37064V
the logic block consumes approximately 50% less power and
slows down by t
LP
.
Output Slew Rate Control
Each output can be configured with either a fast edge rate
(default) for high performance, or a slow edge rate for added
noise reduction. In the fast edge rate mode, outputs switch at
3V/ns max. and in the slow edge rate mode, outputs switch at
1V/ns max. There is a nominal delay for I/Os using the slow
edge rate mode.
In-System Reprogramming
The CY37064V can be programmed in system using IEEE
1149.1 compliant JTAG programming protocol. The
CY37064V can also be programmed on a number of traditional
parallel programmers including Cypress’s
Impulse3
™
pro-
grammer and industry standard third-party programmers. For
an overview of ISR programming, refer to the Ultra37000 Fam-
ily data sheet and for UltraISR cable and software specifica-
tions, refer to InSRkit: ISR Programming data sheet
(CY3600i).
User-Programmable Bus Hold
All outputs of the CY37064V can either be configured into bus
hold mode or left floating. When in bus hold mode, the undriv-
en outputs retain their last value with a weak latch. This feature
allows the designer the flexibility of either eliminating or includ-
ing external pull-up/pull-down resistors. Enabling this feature
affects all I/Os simultaneously.
Design Tools
Development software for the CY37064V is available from Cy-
press’s
Warp
™
or third-party bolt-in software packages as well
as a number of third-party development packages. Please re-
fer to the
Warp
or third-party tool support data sheets for fur-
ther information.
For a more detailed description of the architecture and fea-
tures of the CY37064V see the Ultra37000 family data sheet.
Fully Routable with 100% Logic Utilization
The CY37064V is designed with a robust routing architecture
which allows utilization of the entire device with a fixed pinout.
This makes Ultra37000 optimal for implementing on-board de-
sign changes using ISR without changing pinouts.
Simple Timing Model
The CY37064V features a very simple timing model with pre-
dictable delays. Unlike other high-density CPLD architectures,
there are no hidden speed delays such as fanout effects, inter-
connect delays, or expander delays. The timing model allows
for design changes with ISR without causing changes to sys-
tem performance.
Low-Power Operation
Each Logic Block of the CY37064V can be configured as either
High-Speed (default) or Low-Power. In the Low-Power mode,
2
PRELIMINARY
Pin Configurations
(continued)
100-pin TQFP
Top View
CY37064V
I/O 63
62
61
I/O 60
59
58
57
1
I/O 0
VCC
VCC
56
GND
NC
GND
7
6
5
4
3
VCC
2
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
TCLK
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
CLK
0
/I
0
VCC
N/C
GND
CLK
1
/I
1
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
VCC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TDI
VCC
I/O
55
I/O
54
I/O
53
I/O
52
I/O
51
I/O
50
I/O
49
I/O
48
CLK
3
/I
4
GND
NC
VCC
CLK
2
/I
3
I
/
O
47
I/O
46
I/O
45
I/O
44
I/O
43
I/O
42
I/O
41
I/O
40
GND
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I2
VCC
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
GND
GND
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
VCC
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage........................................... 3.0V to 3.6V
Current into Outputs ...................................................... 8 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
5
VCC
TDO
37064V-5
NC
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