Hitachi Microcomputer Peripheral LSI
HD64461
Windows
®
CE Intelligent Peripheral Controller
ADE-602-076
Rev. 1.0
July 27, 1998
Hitachi Company or Division
Contents
Preface
.....................................................................................................1
Section 1 Features ..........................................................................................3
1.1 CPU Interface .................................................................................................................. 3
1.2 LCD Controller................................................................................................................ 3
1.3 PCMCIA Controller ......................................................................................................... 3
1.4 AFE Interface .................................................................................................................. 3
1.5 GPIO Function................................................................................................................. 3
1.6 Interrupt........................................................................................................................... 4
1.7 Power Management.......................................................................................................... 4
1.8 Timer ............................................................................................................................... 4
1.9 IrDA ................................................................................................................................ 4
1.10 UART ............................................................................................................................ 4
1.11 Package.......................................................................................................................... 4
Section 2 Pin Configuration and Block Diagram ............................................5
2.1 Pin Configuration............................................................................................................. 5
2.2 Block Diagram................................................................................................................. 7
2.3 Physical Address Space Map............................................................................................ 8
2.4 Register Mapping............................................................................................................. 9
2.5 SH7709 CPU Interface Access Timing............................................................................. 10
Section 3 HD64461 Pin Descriptions..............................................................12
Section 4 Color LCD Controller .....................................................................26
4.1 Overview ......................................................................................................................... 26
4.1.1 Features .............................................................................................................. 26
4.1.2 DisplayCapabilities............................................................................................. 26
4.1.3 Hardware Acceleration ....................................................................................... 28
4.1.4 System BUS I/F .................................................................................................. 30
4.1.5 Display Memory I/F............................................................................................ 32
4.2 LCD Controller Control Register ..................................................................................... 33
4.2.1 Base Address Register ........................................................................................ 33
4.2.2 Line Address Offset Register .............................................................................. 34
4.2.3 LCDC Control Register ...................................................................................... 35
4.3 LCD Register................................................................................................................... 46
4.3.1 LCD Display Register......................................................................................... 46
4.3.2 LCD Display Register 2...................................................................................... 47
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4.3.3 LCD Number of Characters in Horizontal Register ............................................. 48
4.3.4 Start Position of Horizontal Register................................................................... 49
4.3.5 Total Vertical Lines Register .............................................................................. 50
4.3.6 Display Vertical Lines Register .......................................................................... 51
4.3.7 Vertical Synchronization Position Register ......................................................... 52
4.3.8 LCD Display Register 3...................................................................................... 52
4.4 CRT Control Register ...................................................................................................... 58
4.4.1 CRTC Total Vertical Lines Register ................................................................... 58
4.4.2 CRTC Vertical Retrace Start Register................................................................. 59
4.4.3 CRTC Vertical Retrace End Register.................................................................. 60
4.5 Palette Register................................................................................................................ 62
4.6 Acceleration Common Registers ...................................................................................... 67
4.7 Line Drawing Registers.................................................................................................... 70
4.8 BitBLT Registers ............................................................................................................. 79
Section 5 PC Card Controller (PCC) .............................................................. 101
5.1 Overview ......................................................................................................................... 101
5.2 Features ........................................................................................................................... 101
5.3 Block Diagram................................................................................................................. 102
5.4 Register Configuration..................................................................................................... 103
5.5 Register Descriptions ....................................................................................................... 104
5.5.1 PCC0 Interface Status Register (PCC0ISR)......................................................... 104
6.5.2 PCC0 General Control Register (PCC0GCR)...................................................... 106
5.5.3 PCC0 Card Status Change Register (PCC0CSCR) .............................................. 108
5.5.4 PCC0 Card Status Change Interrupt Enable Register (PCC0CSCIER) ................ 110
5.5.5 PCC0 Software Control Register (PCC0SCR)..................................................... 112
5.5.6 PCC1 Interface Status Register (PCC1ISR)......................................................... 113
5.5.7 PCC1 General Control Register (PCC1GCR)...................................................... 115
5.5.8 PCC1 Card Status Change Register (PCC1CSCR) .............................................. 117
5.5.9 PCC1 Card Status Change Interrupt Enable Register (PCC1CSCIER) ................ 119
5.5.10 PCC1 Software Control Register (PCC1SCR)................................................... 120
5.5.11 PCC0 Output Pins Control Register (P0OCR) ................................................... 121
5.5.12 PCC1 Output Control Register (P1OCR)........................................................... 122
5.5.13 PC Card General Control Register (PGCR)....................................................... 123
5.6 PCMCIA Address Space .................................................................................................. 124
5.6.1 Continuous 32-MB Area Mode ........................................................................... 124
5.6.2 Continuous 16-MB Area Mode ........................................................................... 126
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Section 6 AFE Interface .................................................................................129
6.1 Overview ......................................................................................................................... 129
6.1.1 Features .............................................................................................................. 129
6.1.2 Block Diagram.................................................................................................... 130
6.2 Register Description......................................................................................................... 132
6.2.1 AFE Control Register (ACTR)............................................................................ 132
6.2.2 AFE Status Register (ASTR)............................................................................... 134
6.2.3 AFE Transmit Data Register (ATXDR) .............................................................. 137
6.2.4 AFE Receive Data Register (ARXDR)................................................................ 137
6.2.5 AFE Transmit Data Buffers (ATXDB0, 1).......................................................... 137
6.2.6 AFE Transmit Shift Register (ATSFTR) ............................................................. 138
6.2.7 AFE Receive Data Buffers (ARXDB0, 1) ........................................................... 138
6.2.8 AFE Receive Shift Register (ARSFTR) .............................................................. 138
6.3 Data Transfer ................................................................................................................... 139
6.3.1 Data Transmit ..................................................................................................... 139
6.3.2 Data Receive ...................................................................................................... 140
6.4 Divider............................................................................................................................. 141
6.5 External Chip Control Signal ........................................................................................... 142
6.6 Interrupt........................................................................................................................... 143
6.7 How to Use the Special Pin (RLYCNT, RING)................................................................ 144
6.7.1 How to Use the RLYCNT Pin............................................................................. 144
6.7.2 How to Use the RING Pin................................................................................... 144
6.8 Attachment ...................................................................................................................... 145
Section 7 Pin Function Controller & I/O Port .................................................147
7.1 Overview ......................................................................................................................... 147
7.1.1 Features .............................................................................................................. 147
7.2 Register Configuration ..................................................................................................... 149
7.3 Register Descriptions ....................................................................................................... 150
7.3.1 Port x (A to D) Data Register (GPADR to GPDDR)............................................ 151
7.3.2 Port Control Register (GPACR to GPDCR) ........................................................ 152
7.3.3 Port Interrupt Control Register (GPAICR−GPDICR) .......................................... 153
7.3.4 Port Interrupt Status Register (GPAISR−GPDISR).............................................. 153
Section 8 Interrupt Controller (INTC) ............................................................155
8.1 Overview ......................................................................................................................... 155
8.1.1 Features .............................................................................................................. 155
8.1.2 Block Diagram.................................................................................................... 156
8.1.3 Pin Configuration................................................................................................ 156
8.1.4 Register Configuration........................................................................................ 156
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