Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> 82801HDOICH8DO

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82801HDOICH8DO: 产品描述Multifunction Peripheral, CMOS, PBGA652, 31 X 31 MM, MICRO, BGA-652; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小7MB，共890页; 制造商Intel(英特尔); 官网地址http://www.intel.com/

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82801HDOICH8DO概述

Multifunction Peripheral, CMOS, PBGA652, 31 X 31 MM, MICRO, BGA-652

82801HDOICH8DO规格参数

参数名称	属性值
厂商名称	Intel(英特尔)
零件包装代码	BGA
包装说明	BGA, BGA652,28X28,40
针数	652
Reach Compliance Code	compliant
其他特性	GAME PORT WITH HIGH DEFINITION AUDIO; SUPPORTS AHCI & RAID FUNCTIONALITY
地址总线宽度	32
边界扫描	NO
总线兼容性	PCI; USB; LPC
最大时钟频率	33 MHz
外部数据总线宽度	32
JESD-30 代码	S-PBGA-B652
长度	31 mm
I/O 线路数量	51
端子数量	652
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA652,28X28,40
封装形状	SQUARE
封装形式	GRID ARRAY
电源	1.5,3.3,5 V
认证状态	Not Qualified
RAM（字数）	256
座面最大高度	2.49 mm
最大供电电压	1.575 V
最小供电电压	1.425 V
标称供电电压	1.5 V
表面贴装	YES
技术	CMOS
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
宽度	31 mm
Base Number Matches	1

文档解析

Intel® I/O Controller Hub 8 (ICH8) 是英特尔芯片组家族的基础版本，设计用于桌面计算平台，提供核心的I/O控制功能。该控制器通过Direct Media Interface (DMI) 接口与主机处理器连接，确保高效的数据传输。它支持多种标准I/O协议，包括PCI Express根端口、USB 2.0和Serial ATA接口，适用于主流PC系统，以可靠性和兼容性为核心。 ICH8集成了六个PCI Express根端口，支持外部设备扩展；配备多个USB 2.0控制器（包括UHCI和EHCI），实现高速外设连接；并提供Serial ATA接口用于存储设备。此外，LPC接口兼容传统外围设备，如Super I/O。电源管理功能遵循ACPI标准，支持S0到S5睡眠状态，包括动态处理器时钟控制和系统唤醒机制。中断处理通过高级可编程中断控制器(APIC)优化，确保系统响应效率。该控制器适用于标准台式机和入门级工作站，提供稳定的I/O性能。它与英特尔处理器兼容，支持多种操作系统环境，包括Windows和Linux。设计重点在于简化系统集成和降低功耗，满足日常计算需求。

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Intel

I/O Controller Hub 8 (ICH8)

Family

Datasheet

– For the Intel

82801HB ICH8, 82801HR ICH8R, 82801HDH ICH8DH,

82801HDO ICH8DO, 82801HBM ICH8M, and 82801HEM ICH8M-E

I/O Controller Hubs

May 2007

Document Number: 313056-003

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL

PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING

TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for

use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

I/O Controller Hub 8 (ICH8) Family chipset component may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I

C bus/protocol and was developed by Intel.

Implementations of the I

C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

Corporation.

Intel

Active Management Technology requires the platform have an Intel

AMT-enabled chipset and network hardware and software, be plugged into a

power source, and have a network connection.

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.

Intel, Intel SpeedStep and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

Intel

ICH8 Family Datasheet

Contents

Introduction

............................................................................................................ 45

1.1

Overview ......................................................................................................... 48

1.2

Intel

ICH8 Family High-Level Component Differences ........................................... 55

Signal Description

................................................................................................... 57

2.1

Direct Media Interface (DMI) to Host Controller ..................................................... 60

2.2

PCI Express* .................................................................................................... 60

2.3

LAN Connect Interface ....................................................................................... 61

2.4

Gigabit LAN Connect Interface ............................................................................ 61

2.5

Firmware Hub Interface...................................................................................... 62

2.6

PCI Interface .................................................................................................... 63

2.7

Serial ATA Interface........................................................................................... 66

2.8

IDE Interface (Mobile Only) ................................................................................ 68

2.9

LPC Interface.................................................................................................... 69

2.10 Interrupt Interface ............................................................................................ 70

2.11 USB Interface ................................................................................................... 71

2.12 Power Management Interface.............................................................................. 72

2.13 Processor Interface............................................................................................ 75

2.14 SMBus Interface................................................................................................ 77

2.15 System Management Interface............................................................................ 77

2.16 Real Time Clock Interface ................................................................................... 78

2.17 Other Clocks..................................................................................................... 79

2.18 Miscellaneous Signals ........................................................................................ 79

2.19 Intel

High Definition Audio Link ......................................................................... 80

2.20 Serial Peripheral Interface (SPI) .......................................................................... 81

2.21 Intel

Quick Resume Technology (Intel

ICH8DH Only) ......................................... 82

2.22 Controller Link .................................................................................................. 82

2.23 Intel

Quiet System Technology (Desktop Only) ................................................... 83

2.24 General Purpose I/O Signals ............................................................................... 83

2.25 Power and Ground............................................................................................. 86

2.26 Pin Straps ........................................................................................................ 88

2.26.1 Functional Straps ................................................................................... 88

2.26.2 External RTC Circuitry ............................................................................. 90

Intel

ICH8 Pin States.............................................................................................

3.1

Integrated Pull-Ups and Pull-Downs ..................................................................... 91

3.2

IDE Integrated Series Termination Resistors (Mobile Only)...................................... 92

3.3

Output and I/O Signals Planes and States............................................................. 92

3.4

Power Planes for Input Signals .......................................................................... 102

Intel

ICH8 and System Clock Domains.................................................................

107

Functional Description

........................................................................................... 109

5.1

PCI-to-PCI Bridge (D30:F0) .............................................................................. 109

5.1.1 PCI Bus Interface ................................................................................. 109

5.1.2 PCI Bridge As an Initiator ...................................................................... 109

5.1.2.1 Memory Reads and Writes........................................................ 110

5.1.2.2 Configuration Reads and Writes ................................................ 110

5.1.2.3 Locked Cycles ........................................................................ 110

5.1.2.4 Target / Master Aborts............................................................. 110

5.1.2.5 Secondary Master Latency Timer............................................... 110

5.1.2.6 Dual Address Cycle (DAC) ........................................................ 110

5.1.2.7 Memory and I/O Decode to PCI................................................. 111

5.1.3 Parity Error Detection and Generation ..................................................... 111

Intel

ICH8 Family Datasheet

5.2

5.3

5.4

5.5

5.1.4 PCIRST# ............................................................................................. 111

5.1.5 Peer Cycles .......................................................................................... 112

5.1.6 PCI-to-PCI Bridge Model ........................................................................ 112

5.1.7 IDSEL to Device Number Mapping ........................................................... 112

5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 113

PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) ................................................ 113

5.2.1 Interrupt Generation ............................................................................. 113

5.2.2 Power Management............................................................................... 114

5.2.2.1 S3/S4/S5 Support ................................................................... 114

5.2.2.2 Resuming from Suspended State ............................................... 114

5.2.2.3 Device Initiated PM_PME Message ............................................. 114

5.2.2.4 SMI/SCI Generation................................................................. 115

5.2.3 SERR# Generation ................................................................................ 115

5.2.4 Hot-Plug .............................................................................................. 115

5.2.4.1 Presence Detection .................................................................. 115

5.2.4.2 Message Generation ................................................................ 116

5.2.4.3 Attention Button Detection ....................................................... 116

5.2.4.4 SMI/SCI Generation................................................................. 117

Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 118

5.3.1 GbE PCI Bus Interface ........................................................................... 118

5.3.1.1 Transaction Layer.................................................................... 118

5.3.1.2 Data Alignment ....................................................................... 118

5.3.1.3 Configuration Request Retry Status ........................................... 119

5.3.2 Error Events and Error Reporting ............................................................ 119

5.3.2.1 Data Parity Error ..................................................................... 119

5.3.2.2 Completion with Unsuccessful Completion Status ......................... 119

5.3.3 Ethernet Interface ................................................................................ 119

5.3.3.1 MAC/LAN Connect Interface ...................................................... 119

5.3.4 PCI Power Management ......................................................................... 120

5.3.4.1 Wake-Up................................................................................ 120

5.3.5 Configurable LEDs................................................................................. 122

5.3.6 Intel

Auto Connect Battery Saver (Mobile Only) ...................................... 122

5.3.6.1 Partial and Full Power Down Options .......................................... 123

5.3.6.2 Intel

ACBS Signal Configurations ............................................. 123

LPC Bridge (w/ System and Management Functions) (D31:F0) ............................... 124

5.4.1 LPC Interface ....................................................................................... 124

5.4.1.1 LPC Cycle Types ...................................................................... 125

5.4.1.2 Start Field Definition ................................................................ 125

5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)..................................... 126

5.4.1.4 Size....................................................................................... 126

5.4.1.5 SYNC..................................................................................... 127

5.4.1.6 SYNC Time-Out ....................................................................... 127

5.4.1.7 SYNC Error Indication .............................................................. 127

5.4.1.8 LFRAME# Usage...................................................................... 127

5.4.1.9 I/O Cycles .............................................................................. 128

5.4.1.10 Bus Master Cycles ................................................................... 128

5.4.1.11 LPC Power Management ........................................................... 128

5.4.1.12 Configuration and Intel

ICH8 Implications................................. 128

DMA Operation (D31:F0) .................................................................................. 129

5.5.1 Channel Priority.................................................................................... 129

5.5.1.1 Fixed Priority .......................................................................... 130

5.5.1.2 Rotating Priority ...................................................................... 130

5.5.2 Address Compatibility Mode ................................................................... 130

5.5.3 Summary of DMA Transfer Sizes ............................................................. 131

5.5.3.1 Address Shifting When Programmed for 16-Bit I/O

Count by Words ...................................................................... 131

5.5.4 Autoinitialize ........................................................................................ 131

Intel

ICH8 Family Datasheet

5.6

5.7

5.8

5.9

5.10

5.5.5 Software Commands............................................................................. 132

LPC DMA ........................................................................................................ 132

5.6.1 Asserting DMA Requests........................................................................ 132

5.6.2 Abandoning DMA Requests .................................................................... 133

5.6.3 General Flow of DMA Transfers............................................................... 133

5.6.4 Terminal Count .................................................................................... 133

5.6.5 Verify Mode ......................................................................................... 134

5.6.6 DMA Request Deassertion...................................................................... 134

5.6.7 SYNC Field / LDRQ# Rules..................................................................... 135

8254 Timers (D31:F0) ..................................................................................... 135

5.7.1 Timer Programming .............................................................................. 136

5.7.2 Reading from the Interval Timer............................................................. 137

5.7.2.1 Simple Read........................................................................... 137

5.7.2.2 Counter Latch Command.......................................................... 137

5.7.2.3 Read Back Command .............................................................. 138

8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 139

5.8.1 Interrupt Handling................................................................................ 140

5.8.1.1 Generating Interrupts.............................................................. 140

5.8.1.2 Acknowledging Interrupts ........................................................ 140

5.8.1.3 Hardware/Software Interrupt Sequence ..................................... 141

5.8.2 Initialization Command Words (ICWx) ..................................................... 141

5.8.2.1 ICW1 .................................................................................... 141

5.8.2.2 ICW2 .................................................................................... 142

5.8.2.3 ICW3 .................................................................................... 142

5.8.2.4 ICW4 .................................................................................... 142

5.8.3 Operation Command Words (OCW) ......................................................... 142

5.8.4 Modes of Operation .............................................................................. 143

5.8.4.1 Fully Nested Mode................................................................... 143

5.8.4.2 Special Fully-Nested Mode........................................................ 143

5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 143

5.8.4.4 Specific Rotation Mode (Specific Priority).................................... 143

5.8.4.5 Poll Mode............................................................................... 144

5.8.4.6 Cascade Mode ........................................................................ 144

5.8.4.7 Edge and Level Triggered Mode ................................................ 144

5.8.4.8 End of Interrupt (EOI) Operations ............................................. 144

5.8.4.9 Normal End of Interrupt........................................................... 144

5.8.4.10 Automatic End of Interrupt Mode .............................................. 145

5.8.5 Masking Interrupts ............................................................................... 145

5.8.5.1 Masking on an Individual Interrupt Request................................ 145

5.8.5.2 Special Mask Mode.................................................................. 145

5.8.6 Steering PCI Interrupts ......................................................................... 145

Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 146

5.9.1 Interrupt Handling................................................................................ 146

5.9.2 Interrupt Mapping ................................................................................ 146

5.9.3 PCI / PCI Express* Message-Based Interrupts .......................................... 147

5.9.4 Front Side Bus Interrupt Delivery ........................................................... 147

5.9.4.1 Edge-Triggered Operation ........................................................ 148

5.9.4.2 Level-Triggered Operation........................................................ 148

5.9.4.3 Registers Associated with Front Side Bus Interrupt Delivery.......... 148

5.9.4.4 Interrupt Message Format ........................................................ 148

Serial Interrupt (D31:F0) ................................................................................. 149

5.10.1 Start Frame......................................................................................... 149

5.10.2 Data Frames........................................................................................ 150

5.10.3 Stop Frame ......................................................................................... 150

5.10.4 Specific Interrupts Not Supported via SERIRQ .......................................... 150

5.10.5 Data Frame Format .............................................................................. 151

Intel

ICH8 Family Datasheet

82801HDOICH8DO相似产品对比

	82801HDOICH8DO	82801HRICH8R	82801HDHICH8DH	82801HBICH8	82801HBMICH8M	82801HEMICH8M-E
描述	Multifunction Peripheral, CMOS, PBGA652, 31 X 31 MM, MICRO, BGA-652	Multifunction Peripheral, CMOS, PBGA652, 31 X 31 MM, MICRO, BGA-652	Multifunction Peripheral, CMOS, PBGA652, 31 X 31 MM, MICRO, BGA-652	Multifunction Peripheral, CMOS, PBGA652, 31 X 31 MM, MICRO, BGA-652	Multifunction Peripheral, CMOS, PBGA652, 31 X 31 MM, MICRO, BGA-652	Multifunction Peripheral, CMOS, PBGA652, 31 X 31 MM, MICRO, BGA-652
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	BGA, BGA652,28X28,40	BGA, BGA652,28X28,40	BGA, BGA652,28X28,40	BGA, BGA652,28X28,40	BGA, BGA676,29X29,40	BGA, BGA676,29X29,40
针数	652	652	652	652	652	652
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
其他特性	GAME PORT WITH HIGH DEFINITION AUDIO; SUPPORTS AHCI & RAID FUNCTIONALITY	GAME PORT WITH HIGH DEFINITION AUDIO; SUPPORTS AHCI & RAID FUNCTIONALITY	GAME PORT WITH HIGH DEFINITION AUDIO; SUPPORTS AHCI & RAID FUNCTIONALITY	GAME PORT WITH HIGH DEFINITION AUDIO; SUPPORTS AHCI & RAID FUNCTIONALITY	GAME PORT WITH HIGH DEFINITION AUDIO; SUPPORTS AHCI & RAID FUNCTIONALITY	GAME PORT WITH HIGH DEFINITION AUDIO; SUPPORTS AHCI & RAID FUNCTIONALITY
地址总线宽度	32	32	32	32	32	32
边界扫描	NO	NO	NO	NO	NO	NO
总线兼容性	PCI; USB; LPC	PCI; USB; LPC	PCI; USB; LPC	PCI; USB; LPC	PCI; USB; LPC	PCI; USB; LPC
最大时钟频率	33 MHz	33 MHz	33 MHz	33 MHz	33 MHz	33 MHz
外部数据总线宽度	32	32	32	32	32	32
JESD-30 代码	S-PBGA-B652	S-PBGA-B652	S-PBGA-B652	S-PBGA-B652	S-PBGA-B652	S-PBGA-B652
长度	31 mm	31 mm	31 mm	31 mm	31 mm	31 mm
I/O 线路数量	51	51	51	51	51	51
端子数量	652	652	652	652	652	652
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	BGA	BGA	BGA	BGA	BGA	BGA
封装等效代码	BGA652,28X28,40	BGA652,28X28,40	BGA652,28X28,40	BGA652,28X28,40	BGA676,29X29,40	BGA676,29X29,40
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
电源	1.5,3.3,5 V	1.5,3.3,5 V	1.5,3.3,5 V	1.5,3.3,5 V	1.05,1.5,3.3,5 V	1.05,1.5,3.3,5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
RAM（字数）	256	256	256	256	256	256
座面最大高度	2.49 mm	2.49 mm	2.49 mm	2.49 mm	2.49 mm	2.49 mm
最大供电电压	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V
最小供电电压	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V
标称供电电压	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
端子形式	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	31 mm	31 mm	31 mm	31 mm	31 mm	31 mm
厂商名称	Intel(英特尔)	Intel(英特尔)	-	Intel(英特尔)	Intel(英特尔)	Intel(英特尔)

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