440V33
PRELIMINARY
CY7C1440V33
CY7C1442V33
CY7C1446V33
1M x 36 / 2M x 18 / 512K x 72 Pipelined SRAM
Features
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Fast clock speed: 300, 250, 200, and 167 MHz
Provide high-performance 3-1-1-1 access rate
Fast access time: 2.3, 2.7, 3.0 and 3.5 ns
Optimal for depth expansion
Single 3.3V –5% and +5% power supply V
DD
Separate V
DDQ
for 3.3V or 2.5V
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip Enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst se-
quence)
Automatic power-down for portable applications
High-density, high-speed packages
JTAG boundary scan for BGA packaging version
Available in 119-bump BG,165-ball FBGA package and
100-pin TQFP packages (CY7C1440V33 and
CY7C1442V33) 209 FBGA package for CY7C1446V33
inputs include all addresses, all data inputs, address-pipelin-
ing Chip Enable (CE), burst control inputs (ADSC, ADSP, and
ADV), write enables (BWa, BWb, BWc, BWd and BWE), and
Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data (DQ
a,b,c,d
) and the data
parity (DP
a,b,c,d
) outputs, enabled by OE, are also asynchro-
nous.
DQ
a,b,c,d
and DP
a,b,c,d
apply to CY7C1440V33, DQ
a,b,c,d,e,f,g,h
and DP
a,b,c,d,e,f,g,h
apply to CY7C1446V33 and DQ
a,b
and
DP
a,b
apply to CY7C1442V33. a, b, c, d, e, f, g, h each are 8
bits wide in the case of DQ and 1 bit wide in the case of DP.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual Byte Write allows individual bytes to be written. BWa
controls DQa and DPa. BWb controls DQb and DPb. BWc con-
trols DQc and DPd. BWd controls DQ and DPd. BWe controls
DQe and DPe. BWf controls DQf and DPf. BWg controls DQg
and DPg. BWh controls DQh and DPh. BWa, BWb, BWc,
BWd, BWe, BWf, BWg and BWh can be active only with BWE
being LOW. GW being LOW causes all bytes to be written.
Write pass-through capability allows written data available at
the output for the immediately next Read cycle. This device
also incorporates a pipelined enable circuit for easy depth ex-
pansion without penalizing system performance.
All inputs and outputs of the CY7C1440V33, CY7C1442V33
and the CY7C1446V33 are JEDEC standard JESD8-5 com-
patible.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced sin-
gle-layer polysilicon, triple-layer metal technology. Each mem-
ory cell consists of six transistors.
The CY7C1440V33, CY7C1442V33, and CY7C1446V33
SRAMs integrate 1,048,576 x 36 / 2,097,152 x18 and 524,288
x 72 SRAM cells with advanced synchronous peripheral cir-
cuitry and a 2-bit counter for internal burst operation. All syn-
chronous inputs are gated by registers controlled by a posi-
tive-edge-triggered Clock Input (CLK). The synchronous
Selection Guide
CY7C1440V33
CY7C1442V33
CY7C1446V33
-300
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Com’l
2.2
TBD
TBD
CY7C1440V33
CY7C1442V33
CY7C1446V33
-250
2.4
TBD
TBD
CY7C1440V33
CY7C1442V33
CY7C1446V33
-200
3.1
TBD
TBD
CY7C1440V33
CY7C1442V33
CY7C1446V33
-167
3.5
TBD
TBD
Cypress Semiconductor Corporation
Document #: 38-05184 Rev. **
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3901 North First Street
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San Jose
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CA 95134
• 408-943-2600
Revised April 8, 2002
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