Octal Transparent Latches with Three-State Outputs
Datasheet
November 2010
www.aeroflex.com/logic
PINOUTS
FEATURES
8 latches in a single package
Three-state bus-driving true outputs
Full parallel access for loading
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 20-pin DIP
- 20-lead flatpack
UT54ACS373 - SMD 5962-96588
UT54ACTS373 - SMD 5962-96589
DESCRIPTION
The UT54ACS373 and the UT54ACTS373 are 8-bit latches
with three-state outputs designed for driving highly capacitive
or relatively low-impedance loads. The device is suitable for
buffer registers, I/O ports, and bidirectional bus drivers.
The eight latches are transparent D latches. While the enable
(C) is high the Q outputs will follow the data (D) inputs. When
the enable is taken low, the Q outputs will be latched at the levels
that were set up at the D inputs.
An output-control input (OC) places the eight outputs in either
a normal logic state (high or low logic levels) or a high-imped-
ance state. The high-impedance third state and increased drive
provide the capability to drive the bus line in a bus-organized
system without need for interface or pull-up components.
The output control OC does not affect the internal operations of
the latches. Old data can be retained or new data can be entered
while the outputs are off.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
OC
L
L
L
H
C
H
H
L
X
nD
H
L
X
X
OUTPUT
nQ
H
L
nQ
0
Z
1
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
OC
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
8Q
8D
7D
7Q
6Q
6D
5D
5Q
C
20-Pin DIP
Top View
OC
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
8Q
8D
7D
7Q
6Q
6D
5D
5Q
C
20-Lead Flatpack
Top View
LOGIC SYMBOL
OC
C
(1)
(11)
EN
C1
1D (3)
(4)
2D
3D (7)
(8)
4D
5D (13)
6D (14)
7D (17)
8D (18)
1D
(2)
1Q
(5)
2Q
(6) 3Q
(9)
(12)
(15)
(16)
(19)
4Q
5Q
6Q
7Q
8Q
1
Note:
1. Data may be latched internally.
LOGIC DIAGRAM
8D
(18)
7D
(17)
6D
(14)
5D
(13)
4D
(8)
3D
(7)
2D
(4)
1D
(3)
C
OC
(11) (1)
DC
Q
DC
Q
DC
Q
DC
Q
D C
Q
D C
Q
D C
Q
DC
Q
(19)
8Q
7Q
(16)
6Q
(15)
5Q
(12)
4Q
(9)
3Q
(6)
2Q
(5)
(2)
1Q
2
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
×C
3
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V
±
10%; V
SS
= 0V
6
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
V
IL
PARAMETER
Low-level input voltage
1
ACTS
ACS
High-level input voltage
1
ACTS
ACS
Input leakage current
ACTS/ACS
Low-level output voltage
3
ACTS
ACS
High-level output voltage
3
ACTS
ACS
Three-state output leakage current
Short-circuit output current
2 ,4
ACTS/ACS
Output current
10
(Sink)
I
OH
Output current
10
(Source)
P
total
I
DDQ
ΔI
DDQ
Power dissipation
2, 8, 9
Quiescent Supply Current
Quiescent Supply Current Delta
ACTS
V
IN
= V
DD
or V
SS
I
OL
= 8.0mA
I
OL
= 100μA
I
OH
= -8.0mA
I
OH
= -100μA
V
O
= V
DD
and V
SS
V
O
= V
DD
and V
SS
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
IN
= V
DD
or V
SS
V
OH
= V
DD
- 0.4V
C
L
= 50pF
V
DD
= 5.5V
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
15
15
pF
pF
1.9
10
1.6
mW/
MHz
μA
mA
-8
mA
.7V
DD
V
DD
- 0.25
-20
20
.5V
DD
.7V
DD
-1
1
CONDITION
MIN
MAX
0.8
.3V
DD
UNIT
V
V
IH
V
I
IN
V
OL
μA
0.40
0.25
V
V
OH
V
μA
I
OZ
I
OS
I
OL
-200
8
200
mA
mA
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤
5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
≤
1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
