HM5425161B Series
HM5425801B Series
HM5425401B Series
256M SSTL_2 interface DDR SDRAM
143 MHz/133 MHz/125 MHz/100 MHz
4-Mword
×
16-bit
×
4-bank/8-Mword
×
8-bit
×
4-bank/
16-Mword
×
4-bit
×
4-bank
E0086H20 (Ver. 2.0)
Jan. 23, 2002
Description
The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM
devices. Read and write operations are performed at the cross points of the CLK and the
CLK.
This high
speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
Features
•
•
•
•
•
•
•
2.5 V power supply
SSTL-2 interface for all inputs and outputs
Clock frequency: 143 MHz/133 MHz/125 MHz/100 MHz (max)
Data inputs, outputs, and DM are synchronized with DQS
4 banks can operate simultaneously and independently
Burst read/write operation
Programmable burst length: 2/4/8
Burst read stop capability
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HM5425161B, HM5425801B, HM5425401B Series
•
Programmable burst sequence
Sequential
Interleave
•
Start addressing capability
Even and Odd
•
Programmable
CAS
latency: 2/2.5
•
8192 refresh cycles: 7.8
µs
(64 ms/8192 cycles)
•
2 variations of refresh
Auto refresh
Self refresh
Ordering Information
Type No.
HM5425161BTT-75A*
1
HM5425161BTT-75B*
2
HM5425161BTT-10*
3
HM5425801BTT-75A*
1
HM5425801BTT-75B*
2
HM5425801BTT-10*
3
HM5425401BTT-75A*
1
HM5425401BTT-75B*
2
HM5425401BTT-10*
3
Frequency
133 MHz
133 MHz
100 MHz
133 MHz
133 MHz
100 MHz
133 MHz
133 MHz
100 MHz
CAS
latency
2.0
2.5
2.0
2.0
2.5
2.0
2.0
2.5
2.0
Package
400-mill 66-pin plastic
TSOP II
Notes: 1. 143 MHz operation at
CAS
latency = 2.5.
2. 100 MHz operation at
CAS
latency = 2.0.
3. 125 MHz operation at
CAS
latency = 2.5.
Data Sheet E0086H20
2
HM5425161B, HM5425801B, HM5425401B Series
Pin Description
Pin name
A0 to A12
Function
Address input
Row address
BA0, BA1
DQ0 to DQ15
DQSU
DQSL
CS
RAS
CAS
WE
DMU
DML
CLK
CLK
CKE
V
REF
V
CC
V
SS
V
CCQ
V
SSQ
NC
Bank select address
Data-input/output
Upper input and output data strobe
Lower input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Upper byte input mask
Lower byte input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
A0 to A12
A0 to A8
Column address
Data Sheet E0086H20
4
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