HM5225645F-B60
HM5225325F-B60
256M LVTTL interface SDRAM
100 MHz
1-Mword
×
64-bit
×
4-bank/2-Mword
×
32-bit
×
4-bank
PC/100 SDRAM
ADE-203-1014C (Z)
Rev. 1.0
Oct. 1, 1999
Description
The Hitachi HM5225645F is a 256-Mbit SDRAM organized as 1048576-word
×
64-bit
×
4-bank. The Hitachi
HM5225325F is a 256-Mbit SDRAM organized as 2097152-word
×
32-bit
×
4-bank. All inputs and outputs
are referred to the rising edge of the clock input. It is packaged in standard 108 bump BGA.
Features
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Single chip wide bit solution (× 64/× 32)
3.3 V power supply
Clock frequency: 100 MHz (max)
LVTTL interface
Extremely small foot print: 1.27 mm pitch
Package: BGA (BP-108)
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 4/8/full page
2 variations of burst sequence
Sequential (BL = 4/8/full page)
Interleave (BL = 4/8)
Programmable
CAS
latency: 2/3
Byte control by DQMB
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HM5225645F-B60, HM5225325F-B60
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Refresh cycles: 4096 refresh cycles/64 ms
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2 variations of refresh
Auto refresh
Self refresh
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Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No.
HM5225645FBP-B60*
HM5225325FBP-B60*
Frequency
100 MHz
100 MHz
CAS
latency
3
3
Package
14 mm
×
22 mm 108 bump BGA (BP-108)
Note: 66 MHz operation at
CAS
latency = 2.
2
HM5225645F-B60, HM5225325F-B60
Pin Description
(HM5225645F)
Pin name
A0 to A13
Function
Address input
Row address
Column address
A0 to A11
A0 to A7
Bank select address A12/A13 (BS)
DQ0 to DQ63
CS
RAS
CAS
WE
DQMB0 to DQMB7
CLK
CKE
V
CC
V
SS
Open
Note:
Data-input/output
Chip select
Row address strobe command
Column address strobe command
Write enable
Byte data mask*
1
Clock input
Clock enable
Power supply
Ground
Open*
2
1. DQMB0: DQ0 to DQ7
DQMB1: DQ8 to DQ15
DQMB2: DQ16 to DQ23
DQMB3: DQ24 to DQ31
DQMB4: DQ32 to DQ39
DQMB5: DQ40 to DQ47
DQMB6: DQ48 to DQ55
DQMB7: DQ56 to DQ63
2. Don’t connect. Internally connected with die.
4