CY2071A
Single-PLL General-Purpose
EPROM Programmable Clock Generator
Features
• Single phase-locked loop architecture
• EPROM programmability
• Factory-programmable (CY2071A, CY2071AI) or
field-programmable (CY2071AF, CY2071AFI) device
options
• Up to three configurable outputs
• Low skew, low jitter, high-accuracy outputs
• Internal loop filter
• Power management (OE)
• Frequency select options
• Configurable 5V or 3.3V operation
• 8-pin 150-mil SOIC package
Benefits
•
•
•
•
•
•
•
•
•
•
Generates a custom frequency from an external source
Easy customization and fast turnaround
Programming support available for all opportunities
Generates three related frequencies from a single device
Meets critical industry standard timing requirements
Alleviates the need for external components
Supports low-power applications
Three outputs with two user-selectable frequencies
Supports industry standard design platforms
Industry standard packaging saves on board space
Selector Guide
Part Number
CY2071A
CY2071AI
CY2071AF
CY2071AFI
Outputs
3
3
3
3
Input Frequency Range
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
Output Frequency Range
500 kHz–130 MHz (5V)
500 kHz–100 MHz (3.3V)
500 kHz–100 MHz (5V)
500 kHz–80 MHz (3.3V)
500 kHz–100 MHz (5V)
500 kHz–80 MHz (3.3V)
500 kHz–90 MHz (5V)
500 kHz–66.6 MHz (3.3V)
Specifics
Factory Programmable
Commercial Temperature
Factory Programmable
Industrial Temperature
Field Programmable
Commercial Temperature
Field Programmable
Industrial Temperature
Logic Block Diagram for CY2071A
XTALIN
XTALOUT
PLL
Block
REFERENCE
OSCILLATOR
CLKA
EPROM-
Configurable
Multiplexer
and Divide
Logic
CLKB
CLKC
OE / FS
Pin Configuration
8-pin SOIC
Top View
CLKA
GND
XTALIN
XTALOUT
1
2
3
4
8
7
6
5
OE/FS
VDD
CLKC
CLKB
Cypress Semiconductor Corporation
Document #: 38-07139 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 3, 2006
CY2071A
Pin Summary
Name
CLKA
GND
XTALIN
CLKB
CLKC
V
DD
OE / FS
[1]
Number
1
2
3
4
5
6
7
8
Configurable Clock Output
Ground
Description
Reference Crystal Input or External Reference Clock Input
Reference Crystal Feedback
Configurable Clock Output
Configurable Clock Output
Voltage Supply
Output Control Pin, either Output Enable or Frequency Select Input
(Active HIGH, internal pull-up resistor to V
DD
)
XTALOUT
[1, 2]
Functional Description
The CY2071A is a general-purpose clock synthesizer
designed for use in applications such as modems, disk drives,
CD-ROM drives, video CD players, games, set-top boxes, and
data/telecommunications. The device offers up to three config-
urable clock outputs in an 8-pin, 150-mil SOIC package and
can operate off either a 3.3V or 5V power supply. The on-chip
reference oscillator is designed for 10 MHz to 25 MHz crystals.
Alternatively, an external reference clock of frequency
between 1 MHz and 30 MHz can be used.
The CY2071A has one PLL and outputs three factory-EPROM
configurable clocks: CLKA, CLKB, and CLKC. The output
clocks can originate either from the PLL or the reference, or
selected dividers thereof. Additionally, pin 8 can be configured
to be an Output Enable or a Select input.
The CY2071A can replace multiple Metal Can Oscillators
(MCO) in a synchronous system, providing cost and board
space savings to the manufacturer. Hence, these devices are
ideally suited for applications that require multiple, accurate,
and stable clocks synthesized from low-cost generators in
small packages. A hard-disk drive is an example of such an
application. In this case, CLKA drives the PLL in the Read
Controller, while CLKB and CLKC drive the MCU and
associated sequencers.
CyClocks Software
CyClocks™ is an easy-to-use software application that allows
you to configure any one of the EPROM-Programmable
Clocks offered by Cypress. You may specify the input
frequency, PLL and output frequencies, and different
functional options. Note the output frequency ranges in this
data sheet when specifying them in CyClocks to ensure that
you stay within the limits. You can download a copy of
CyClocks free on the Cypress Semiconductor Corporation
web site at www.cypress.com.
Use the CY2081 for applications that require unrelated output
frequencies. Use the CY2291, CY2292, or CY2907 for appli-
cations that require more than three output clocks.
Cypress FTG Programmer
The Cypress Frequency Timing Generator (FTG) Programmer
is a portable programmer designed to custom program our
family of EPROM Field Programmable Clock Devices. The
FTG programmers connect to a PC serial port and allow users
of CyClocks software to easily program any of the CY2291F,
CY2292F, CY2071AF, and CY2907F devices. The ordering
code for the Cypress FTG Programmer is CY3670.
Absolute Maximum Conditions
[3, 4]
Parameter
V
DD
V
IN
T
S
T
A
T
J
ESD
HBM
Description
Analog Supply Voltage
DC Input Voltage
Temperature, Storage
Temperature, Maximum Soldering (10 sec)
Temperature, Junction
ESD Protection (Human Body Model)
Non-functional
Functional
Functional
MIL-STD-883, Method 3015
Condition
Min.
–0.5
–0.5
–65
–
–
2000
Max.
7.0
150
260
150
–
Unit
V
°C
°C
°C
V
V
DD
+ 0.5 VDC
Notes
1. For best accuracy, use a parallel-resonant crystal, C
L
= 17 pF.
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to an external crystal).
3. Stresses greater than those listed in this table may cause permanent damage to the device.
4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07139 Rev. *D
Page 2 of 9
CY2071A
Operating Conditions
[5]
Parameter
V
DD
V
DD
T
A
C
L
f
REF
t
PU
Supply Voltage, 5.0V Operation
Supply Voltage, 3.3V Operation
Commercial Operating Temperature, Ambient
Industrial Operating Temperature, Ambient
Max. Load Capacitance per Output (5V Operation)
Max. Load Capacitance per Output (3.3V Operation)
External Reference Crystal
External Reference
Clock
[6, 7]
Power-up time for all VDDs to reach minimum specified voltage (power ramps
must be monotonic)
Description
Min.
4.5
3.0
0
–40
–
–
10.0
1.0
0.05
Max.
5.5
3.6
70
85
25
15
25.0
30.0
50
Unit
V
V
°C
°C
pF
pF
MHz
MHz
ms
Electrical Characteristics, Commercial 5.0V:
V
DD
= 5V ±10%, T
A
= 0°C to +70°C
[8]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
Description
HIGH-Level Output Voltage
LOW-Level Output Voltage
HIGH-Level Input
Voltage
[9]
Voltage
[9]
LOW-Level Output
Input LOW Current
Output Leakage Current
V
DD
Supply Current
[10]
I
OH
= –4.0 mA
I
OL
= 4.0 mA
Except Crystal Pins
Except Crystal Pins
V
IN
= V
DD
– 0.5V
V
IN
= 0.5V
Three State Outputs
V
DD
= V
DD
max. 5V operation, C
L
= 25 pF
Conditions
Min.
2.4
–
2.0
–
–
–
–
Typ.
–
–
–
–
–
–
–
40
Max.
–
0.4
–
0.8
10
150
250
60
Unit
V
V
V
V
µA
µA
µA
mA
Input HIGH Current
Electrical Characteristics, Commercial 3.3V:
V
DD
= 3.3V ±10%, T
A
= 0°C to 70°C
[8]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
Description
HIGH-Level Output Voltage
LOW-Level Output Voltage
HIGH-Level Input Voltage
LOW-Level Output
Input LOW Current
Output Leakage Current
V
DD
Supply Current
[10]
Input HIGH Current
[9]
Conditions
I
OH
= –4.0 mA
I
OL
= 4.0 mA
Except Crystal Pins
Except Crystal Pins
V
IN
= V
DD
– 0.5V
V
IN
= 0.5V
Three State Outputs
V
DD
= V
DD
max. 3.3V operation, C
L
= 15 pF
Min.
2.4
–
2.0
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
24
Max.
–
0.4
–
0.8
10
150
250
40
Unit
V
V
V
V
µA
µA
µA
mA
Voltage
[9]
Notes:
5. Electrical parameters are guaranteed with these operating conditions. Values for 3.3V operation are shown in parentheses.
6. External input reference clock must have a duty cycle between 40% and 60%, measured at V
DD
/2.
7. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock.
8. See “CY2071A and CY2907 Clock Generators” Application Note for important customer clarification.
9. Xtal inputs have CMOS thresholds.
10. Load = max, typical configuration, f
REF
= 14.318 MHz. Specific configurations may vary. A close approximation of I
DD
can be derived by the following formula:
I
DD
(mA) = V
DD
*(6.25+(0.055*F
REF
) + (0.0017*C
LOAD
*(F
CLKA
+F
CLKB
+F
CLKC
))). C
LOAD
is specified in pF and F is specified in MHz.
Document #: 38-07139 Rev. *D
Page 3 of 9
CY2071A
Electrical Characteristics, Industrial 5.0V:
V
DD
= 5.0V ±10%, T
A
= –40°C to 85°C
[8]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
Description
HIGH-Level Output Voltage
LOW-Level Output Voltage
HIGH-Level Input Voltage
[9]
LOW-Level Output Voltage
[9]
Input HIGH Current
Input LOW Current
Output Leakage Current
V
DD
Supply
Current
[10]
I
OH
= –4.0 mA
I
OL
= 4.0 mA
Except Crystal Pins
Except Crystal Pins
V
IN
= V
DD
– 0.5V
V
IN
= 0.5V
Three State Outputs
V
DD
= V
DD
max. 5V operation, C
L
= 25 pF
40
2.0
0.8
10
150
250
75
Conditions
Min.
2.4
0.4
Typ.
Max.
Unit
V
V
V
V
µA
µA
µA
mA
Electrical Characteristics, Industrial 3.3V
V
DD
=3.3V ±10%, T
A
= –40°C to +85°C
[8]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
Description
HIGH-Level Output Voltage
LOW-Level Output Voltage
HIGH-Level Input Voltage
[9]
LOW-Level Output Voltage
[9]
Input HIGH Current
Input LOW Current
Output Leakage Current
V
DD
Supply Current
[10]
I
OH
= –4.0 mA
I
OL
= 4.0 mA
Except Crystal Pins
Except Crystal Pins
V
IN
= V
DD
– 0.5V
V
IN
= 0.5V
Three State Outputs
V
DD
= V
DD
max. 3.3V operation,
C
L
=
15 pF
24
2.0
0.8
10
150
250
50
Conditions
Min.
2.4
0.4
Typ.
Max.
Unit
V
V
V
V
µA
µA
µA
mA
Switching Characteristics, Commercial 5.0V
[11]
Parameter
t
1
Name
Output Period
Description
Clock output range 5V
operation 25-pF load
CY2071A
CY2071AF
t
1A
t
1B
t
1C
Clock Jitter
Clock Jitter
Clock Jitter
[12]
Output Duty Cycle
Peak-to-peak period jitter (t
1
max. – t
1
min.),
% of clock period, f
OUT
≤
16 MHz
Peak-to-peak period jitter
(16 MHz
≤
f
OUT
≤
50 MHz)
Peak-to-peak period jitter (f
OUT
> 50 MHz)
Duty cycle
[13, 14]
for outputs, (t
2
÷
t
1
)
f
OUT
≤
60 MHz
45%
40%
Min.
7.692
[130 MHz]
10
[100 MHz]
0.8
350
250
50%
50%
1.5
1.5
Typ.
Max.
2000
[500 kHz]
2000
[500 kHz]
1
500
350
55%
60%
2.5
2.5
0.5
ns
ns
ns
Unit
ns
ns
%
ps
ps
Output Duty Cycle
[12]
Duty cycle
[14]
for outputs, (t
2
÷
t
1
),
f
OUT
> 60 MHz
t
3
t
4
t
5
Rise Time
[12]
Fall Time
Skew
[12]
Output clock rise time
Output clock fall time
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
Notes:
11. Guaranteed by design, not 100% tested.
12. When the output clock frequency is between 100 MHz and 130 MHz at 5V, the maximum capacitive load for these measurements is 15 pF.
13. Reference Output duty cycle depends on XTALIN duty cycle.
14. Measured at 1.4V.
Document #: 38-07139 Rev. *D
Page 4 of 9
CY2071A
Switching Characteristics, Commercial 3.3V
[11]
Parameter
t
1
Name
Output Period
Description
Clock output range 3.3V operation CY2071AS
15-pF load
CY2071AF
Peak-to-peak period jitter (t
1
max. – t
1
min.), % of
clock period, f
OUT
≤
16 MHz
Peak-to-peak period jitter
(16 MHz
≤
f
OUT
≤
50 MHz)
Peak-to-peak period jitter (f
OUT
> 50 MHz)
Duty cycle
[13, 14]
for outputs, (t
2
÷
t
1
)
f
OUT
≤
60 MHz
Duty cycle
[14]
for outputs, (t
2
÷
t
1
),
f
OUT
> 60 MHz
Output clock rise time
Output clock fall time
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
45%
40%
Min.
10
[100 MHz]
12.50
[80 MHz]
Typ.
Max.
2000
[500 kHz]
2000
[500 kHz]
Unit
ns
ns
%
ps
ps
t
1A
t
1B
t
1C
Clock Jitter
Clock Jitter
Clock Jitter
[12]
Output Duty Cycle
Output Duty
Cycle
[12]
0.8
350
250
50%
50%
1.5
1.5
1
500
350
55%
60%
2.5
2.5
0.5
t
3
t
4
t
5
Rise Time
[12]
Fall Time
[12]
Skew
ns
ns
ns
Switching Characteristics, Industrial 5.0V
[11]
Parameter
t
1
Name
Output Period
Description
Clock output range 5.0V operation CY2071AI
25-pF load
CY2071AFI
t
1A
Clock Jitter
Peak-to-peak period jitter (t
1
max. –
t
1
min.),
% of clock period, f
OUT
≤
16 MHz
Peak-to-peak period jitter
(16 MHz
≤
f
OUT
≤
50 MHz)
Peak-to-peak period jitter
(f
OUT
> 50 MHz)
Duty cycle
[13, 14]
for outputs, (t
2
÷
t
1
)
f
OUT
≤
60 MHz
Duty cycle
[14]
for outputs, (t
2
÷
t
1
),
f
OUT
>
60 MHz
Output clock rise time
Output clock fall time
Skew delay between any two
outputs with identical frequencies
(generated by the PLL)
45%
40%
Min.
10
[100 MHz]
11.1
[90 MHz]
0.8
Typ.
Max.
2000
[500 kHz]
2000
[500 kHz]
1
Unit
ns
ns
%
t
1B
t
1C
Clock Jitter
Clock Jitter
[12]
Output Duty Cycle
Output Duty
Cycle
[12]
350
250
50%
50%
1.5
1.5
500
350
55%
60%
2.5
2.5
0.5
ps
ps
t
3
t
4
t
5
Rise time
[12]
Fall time
Skew
[12]
ns
ns
ns
Document #: 38-07139 Rev. *D
Page 5 of 9
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