UC1825-SP
www.ti.com...............................................................................................................................................................................................
SLUS870 – JANUARY 2009
RAD-TOLERANT CLASS V, HIGH-SPEED PWM CONTROLLER
1
FEATURES
QML-V Qualified, SMD 5962-87681
Rad-Tolerant: 30 kRad (Si) TID
(1)
Compatible With Voltage- or Current-Mode
Topologies
Practical Operation Switching Frequencies to
1 MHz
50-ns Propagation Delay-to-Output
High-Current Dual Totem Pole Outputs
(1.5 A Peak)
Wide Bandwidth Error Amplifier
Fully Latched Logic With Double-Pulse
Suppression
Pulse-by-Pulse Current Limiting
Soft Start/Maximum Duty-Cycle Control
Undervoltage Lockout With Hysteresis
Low Start-Up Current (1.1 mA)
•
•
•
•
•
•
•
•
•
•
•
•
(1)
DESCRIPTION
The UC1825 PWM control device is optimized for
high-frequency switched mode power supply
applications. Particular care was given to minimizing
propagation delays through the comparators and
logic circuitry while maximizing bandwidth and slew
rate of the error amplifier. This controller is designed
for use in either current-mode or voltage mode
systems with the capability for input voltage
feed-forward.
Protection circuitry includes a current limit comparator
with a 1-V threshold, a TTL compatible shutdown
port, and a soft start pin which will double as a
maximum duty-cycle clamp. The logic is fully latched
to provide jitter-free operation and prohibit multiple
pulses at an output. An undervoltage lockout section
with 800 mV of hysteresis assures low start up
current. During undervoltage lockout, the outputs are
high impedance.
This device features totem pole outputs designed to
source and sink high peak currents from capacitive
loads, such as the gate of a power MOSFET. The on
state is designed as a high level.
Radiation tolerance is a typical value based upon initial device
qualification with dose rate = 10 mrad/sec. Radiation Lot
Acceptance Testing is available - contact factory for details.
BLOCK DIAGRAM
CLOCK
R
T
C
T
RAMP
4
5
OSC
6
1.25 V
7
S
Wide Bandwidth
Error Amp.
Error
Amp
NI
INV
2
1
+
−
Inhibit
E/A Out 3
V
IN
9
µA
Toggler F/F
Soft Start 8
I
LIM
CPRTR
1V
I
LIM
/ SD
9
1.4 V
Output
Inhibit
V
CC
15
9V
GND 10
V
CC
Good
UVLO
Gate
REF
Gen
Internal
Bias
4V
V
REF
Good
16
V
REF
Shutdown
CPRTR
13 Vc
11 Out A
T
14 Out B
12 Pwr GND
PWM Latch
(Set Dom.)
R
VDG−92032−2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
UC1825-SP
SLUS870 – JANUARY 2009...............................................................................................................................................................................................
www.ti.com
This device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
T
A
–55°C to 125°C
(1)
(2)
PACKAGE
(2)
CDIP – J
LCCC – FK
ORDERABLE PART NUMBER
5962-8768104VEA
5962-8768104V2A
TOP-SIDE MARKING
UC1825J-SP
UC1825FK-SP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at
www.ti.com.
Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
2
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Product Folder Link(s):
UC1825-SP
Copyright © 2009, Texas Instruments Incorporated
UC1825-SP
www.ti.com...............................................................................................................................................................................................
SLUS870 – JANUARY 2009
J PACKAGE
(TOP VIEW)
FK PACKAGE
(TOP VIEW)
INV
NI
E/A Out
Clock
R
T
C
T
Ramp
Soft Start
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
REF
5.1 V
V
CC
Out B
V
C
Pwr Gnd
Out A
Gnd
ILIM/SD
E/A Out
Clock
NC
R
T
C
T
3 2
4
5
6
7
8
NI
INV
NC
V REF 5.1 V
VCC
1 20 19
18
17
16
15
14
9 10 11 12 13
Out B
V
C
NC
Pwr Gnd
Out A
Table 1. TERMINAL FUNCTIONS
NAME
Clock
C
T
E/A Out
Gnd
ILIM/SD
INV
NC
NI
Out A
Out B
Pwr Gnd
Ramp
R
T
Soft Start
V
C
V
CC
V
REF
5.1 V
2
11
14
12
7
5
8
13
15
16
NO.
J
4
6
3
10
9
1
FK
5
8
4
13
12
2
1, 6, 11, 16
3
14
18
15
9
7
10
17
19
20
I/O
O
I
O
-
I
I
-
I
O
O
-
I
I
I
-
-
O
Output of the internal oscillator
Timing capacitor connection pin for oscillator frequency programming. The timing capacitor
should be connected to the device ground using minimal trace length.
Output of the error amplifier for compensation
Analog ground return pin
Input to the current limit comparator and the shutdown comparator
Inverting input to the error amplifier
No connection
Non-inverting input to the error amplifier
High-current totem pole output A of the on-chip drive stage
High-current totem pole output B of the on-chip drive stage
Ground return pin for the output driver stage
Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage
mode operation this serves as the input voltage feed-forward function by using the CT
ramp. In peak current mode operation, this serves as the slope compensation input.
Timing resistor connection pin for oscillator frequency programming
Soft-start input pin which also doubles as the maximum duty cycle clamp
Power supply pin for the output stage. This pin should be bypassed with a 0.1-µF
monolithic ceramic low ESL capacitor with minimal trace lengths.
Power supply pin for the device. This pin should be bypassed with a 0.1-µF monolithic
ceramic low ESL capacitor with minimal trace lengths.
5.1-V reference. For stability, the reference should be bypassed with a 0.1-µF monolithic
ceramic low ESL capacitor and minimal trace length to the ground plane.
DESCRIPTION
Copyright © 2009, Texas Instruments Incorporated
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UC1825-SP
Ramp
Soft Start
NC
ILIM/SD
Gnd
3
UC1825-SP
SLUS870 – JANUARY 2009...............................................................................................................................................................................................
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
UNIT
Supply voltage
Output current, source or sink, Out A, Out B
Analog inputs
Clock output current
Error amplifier output current
Soft-start sink current
Oscillator charging current
Power dissipation
Storage temperature range
Lead temperature (soldering, 10 seconds)
(1)
V
C
, V
CC
DC
Pulse (0.5
µs)
INV, NI, Ramp
Soft Start, ILIM/SD
Clock
E/A Out
Soft Start
R
T
30
0.5
2.0
–0.3 to 7
–0.3 to 6
–5
5
20
–5
1
–65 to 150
300
W
°C
mA
V
A
V
All voltages are with respect to GND; all currents are positive into, negative out of part; pin numbers refer to DIL-16 package.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (T
A
= T
J
= –55°C to 125°C), unless otherwise noted.
MIN
V
CC
Supply voltage
Sink/source output current (continuous or time average)
Reference load current
10
0
0
MAX
30
100
10
UNIT
V
mA
mA
THERMAL RATINGS TABLE
PACKAGE
DIL-16 (J)
LCC-20 (FK)
(1)
θ
JA
(°C/W)
80–120
70–80
θ
JC
(°C/W)
28
(1)
20
(1)
θ
JC
data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states that the baseline values shown are worst case
(mean + 2s) for a 60 × 60 mil microcircit device silicon die and applicable for devices with die sizes up to 14400 square mils. For device
die sizes greater than 14400 square mils use the following values; dual-in-line, 11°C/W; flat pack 10°C/W; pin grid array, 10°C/W.
4
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Product Folder Link(s):
UC1825-SP
Copyright © 2009, Texas Instruments Incorporated
UC1825-SP
www.ti.com...............................................................................................................................................................................................
SLUS870 – JANUARY 2009
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply for R
T
= 3.65 kΩ, C
T
= 1 nF, V
CC
= 15 V, –55°C < T
A
< 125°C, T
A
= T
J
PARAMETERS
REFERENCE
Output voltage
Line regulation
Load regulation
Total output variation
Output noise voltage
Short-circuit current
OSCILLATOR SECTION
Initial accuracy
Voltage stability
Temperature stability
Total variation
Clock out high
Clock out low
Ramp peak
(1)
(1)
TEST CONDITIONS
T
J
= 25°C, I
O
= 1 mA
10 V < V
CC
< 30 V
1 mA < I
O
< 10 mA
Line, load, temperature
10 Hz < f < 10 kHz
V
REF
= 0 V
T
J
= 25°C
10 V < V
CC
< 30 V
T
MIN
< T
A
< T
MAX
Line, Temperature
MIN
5.05
TYP
5.10
2
5
MAX
5.15
20
20
5.2
UNIT
V
mV
mV
V
µV
mA
kHz
5.0
50
–15
360
–50
400
0.2%
5%
340
3.9
2.6
0.7
1.6
4.5
2.3
2.8
1.0
1.8
–100
440
2%
460
2.9
3.0
1.25
2.1
10
kHz
V
V
V
V
V
mV
µA
µA
dB
dB
dB
mA
mA
Ramp valley
Ramp valley to peak
(1)
ERROR AMPLIFIER
Input offset voltage
Input bias current
Input offset current
Open-loop gain
CMRR
PSRR
Output sink current
Output source current
Output high voltage
Output low voltage
Gain bandwidth product
(1)
Slew rate
(1)
0.6
0.1
1 V < V
O
< 4 V
1.5 V < V
CM
< 5.5 V
10 V < V
CC
< 30 V
V
E/AOut
= 1 V
V
E/AOut
= 4 V
I
E/AOut
= –0.5 mA
I
E/AOut
= 1 mA
f = 200 kHz
60
75
85
1
–0.5
4.0
0
5
4
V
Ramp
= 0 V
0%
V
Ramp
= 0 V
1.1
1.25
50
V
Soft
V
Soft
= 0.5 V
=1V
3
1
9
95
95
110
2.5
–1.3
4.7
0.5
10.5
9
–1
3
1
5.0
1.0
V
V
MHz
V/µs
PWM COMPARATOR
Ramp bias current
Duty cycle range
E/A out zero dc threshold
Delay to output
SOFT-START
Charge current
Discharge current
CURRENT LIMIT/SHUTDOWN
Current limit/shutdown bias current
Current limit threshold
Shutdown threshold
Delay to output
(1)
(1)
Parameters ensured by design and/or characterization, if not production tested.
0 < V
ILIM/SD
< 4 V
0.9
1.25
1.0
1.40
50
15
1.1
1.55
80
µA
V
V
ns
Start
Start
(1)
–5
80%
µA
V
80
20
ns
µA
mA
Copyright © 2009, Texas Instruments Incorporated
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UC1825-SP
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