Hitachi SuperH RISC engine
SH7727
Hardware Manual
ADE-602-209B
Rev. 3.0
2/28/2002
Hitachi, Ltd.
Cautions
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contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
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life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
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Preface
The SH7727 microprocessor incorporates the 32-bit SH-3 CPU and is also equipped with
peripheral functions necessary for configuring a user system.
The SH7727 is built in with a variety of peripheral functions such as cache memory, memory
management unit (MMU), interrupt controller, timers, three serial communication interfaces (SCI,
SCIF, SIOF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and
AFE interface. The SH7727 can be used in a variety of applications that demand a high-speed
microcomputer with low power consumption.
Target Readers:
This manual is designed for use by people who design application systems using
the SH7727.
To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is
required.
Purpose:
This manual provides the information of the hardware functions and electrical
characteristics of the SH7727.
The SH-3, SH-3E, SH3-DSP Programming Manual contains detailed information of executable
instructions. Please read the Programming Manual together with this manual.
How to Use the Book:
To understand general functions
Read the manual from the beginning.
The manual explains the CPU, system control functions, peripheral functions and electrical
characteristics in that order.
To understanding CPU functions
Refer to the separate SH-3, SH-3E, SH3-DSP Programming Manual.
Explanatory Note:
Bit sequence: upper bit at left, and lower bit at right
List of Related Documents:
The latest documents are available on our Web site. Please make
sure that you have the latest version. (http://www.hitachisemiconductor.com/)
User manuals for SH7727
Name of Document
SH7727 Hardware Manual
SH-3, SH-3E, SH3-DSP Programming Manual
Document No.
This manual
ADE-602-096
Rev. 3.0, 02/02, page iii of xxiv
User manuals for development tools
Name of Document
C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual
Simulator/Debugger User’s Manual
Hitachi Embedded Workshop User’s Manual
Document No.
ADE-702-246
ADE-702-186
ADE-702-201
Rev. 3.0, 02/02, page iv of xxiv
List of Items Revised or Added for This Version
Section
7.1.2 Block Diagram
7.3.10 Interrupt Request
Register 3 (IRR3)
12.2.5 Individual Memory
Control Register (MCR)
12.3.4 Synchronous DRAM
Interface
Page
160
186
290
Bits 15 and 14—RAS
Precharge Time (TPC1,
TPC0)
Address Multiplexing
Table 12.12 Relationship
between Synchronous
DRAM type, bus width and
AMX
Item
Figure 7.1 INTC Block
Diagram
Description
(see Manual for details)
Amended
Names of bits 6 and 5
amended
Description amended
319
320
A25–A16 amended to
A25–A17
Bus width 16 bits,
memory type 256 Mbits
external address pin A13
amended to A22
Bus width 32 bits,
memory type 256 Mbits
external address pin A14
amended to A23
Bus width 16 bits,
memory type 128 Mbits
external address pin A15
amended to A24
20.2.7 FIFO Control
Register (SIFCTR)
20.3.5 Control Data
Interface
589
Modified R/W status of
bits 15, 12, 10, 9, 8, 6,
and 5
Figure 20.8 Control Data
Interface (Secondary FS)
TDRE=1, RDRE=1,
CD1E=1 amended to
TDRE=0, RDRE=0,
CD1E=0
TDRE=1, RDRE=1,
CD1E=1 amended to
TDRE=0, RDRE=0,
CD1E=0
TDRE=1, RDRE=1
amended to TDRE=0,
RDRE=0
607
20.3.8 Interrupt
617
Figure 20.13 Transmit or
Receive Timing (8 bits
monaural—1)
Figure 20.15 Transmit or
Receive Timing (16 bits
monaural—1)
618
Rev. 3.0, 02/02, page v of xxiv
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