3.3V 155 Mbps ATM SAR CONTROLLER
WITH ABR SUPPORT FOR PCI-BASED
NETWORKING APPLICATIONS
Integrated Device Technology, Inc.
IDT77V252
KEY FEATURES
• Full-duplex Segmentation and Reassembly (SAR) at
155 Mbps "wire-speed" (310 Mbps aggregate speed)
• Operates with ATM Networks up to 155.52 Mbps
• Stand-alone Controller: Embedded Processor not required
• Performs ATM Layer Protocol Functions
• Supports AAL5, AAL3/4, AAL0 and Raw Cell Formats
• Supports Constant Bit Rate (CBR), Variable Bit Rate
(VBR), and Unassigned Bit Rate (UBR), and Available Bit
Rate (ABR) Service Classes
• Segments and Reassembles CS-PDUs into Host Memory
• Up to 16K Open Transmit Connections
• Up to 16K Simultaneous Receive Connections
• ABR, VBR, UBR Selectable per VC Time-out
• Automatic AAL5 Padding
• Four Buffer Pools for Independent or Chained Reassembly
• Buffer Management Options for MPEG Operation
• Supports Any Buffer Alignment Condition
• Free Bufffer Queues Mapped Into PCI Memory Space
• Rx FIFO Size (Configurable to 1024 Kbytes)
• Configurable Transmit FIFO Depth for Reduced Latency
• Supports Big and Little Endian Data Transfers
• UTOPIA Master/Slave Mode
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Null Cell Disable Option During Transmit
RM Cell Handling
Option to Select ITU or ATM Null Cell Format
NAND, Scan, and Output Test Modes
UTOPIA Level 1 Interface to PHY
Utility Bus Interface for PHY Management
Serial EEPROM Interface
EPROM Interface
PCI 2.1 Compliant
Compact PCI R1.0 Hot Swap Friendly Compliant
UNI 3.1, TM 4.0 Compliant
Meets PCI Bus Power Management and Interface Specifi-
cation Revision 1.1
Pin Compatible with IDT 77211/77252 SAR
Software Compatible with the IDT 77252
Commercial and Industrial Temprature Ranges
208-Lead PQFP Package (28 x 28mm)
Software Drivers:
SARWIN 2 Demonstration Program
NDIS Driver
Vx Works (3rd party)
Linux (3rd party)
SYSTEM-LEVEL FUNCTIONAL BLOCK DIAGRAM
16K x 32 to 512K x 32
SR A M
PCI BUS
8
PROM
32
Rx U TO PIA Bus
PCI Interface
8
33M H Z
32
IDT77V252
155Mbps
P C I AT M
ABR SAR
155Mbps
P HY
2
2
Tx UTO PIA Bus
8
U tility B us
8
80.0M HZ OSC.
EEPROM
5350 drw 01
NICStAR is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
©2001 Integrated Device Technology, Inc.
DSC-5350/8
JANUARY 2001
1
IDT77V252 155Mb/s ATM Segmentation & Reassembly (SAR) Controller
with ABR for the PCI Local Bus
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
DESCRIPTION
The IDT77V252 NICStAR
™
is a member of IDT's family of
products for Asynchronous Transfer Mode (ATM) networks.
The ABR SAR performs both the ATM Adaptation Layer (AAL)
Segmentation and Reassembly (SAR) function and the ATM
layer protocol functions.
A Network Interface Card (NIC) or internetworking product
based on the ABR SAR uses host memory, rather than local
memory, to reassemble Convergence Sublayer Protocol
Data Units (CS-PDUs) from ATM cell payloads received from
the network. When transmitting, as CS-PDUs become ready,
they are queued in host memory and segmented by the ABR
SAR into ATM cell payloads. From this, the ABR SAR then
creates complete 53-byte ATM cells which are sent through
the network. The ABR SAR's on-chip PCI bus master
interface provides efficient, low latency DMA transfers with
the host system, while its UTOPIA interface provides direct
connection to PHY components used in 25.6 Mbps to 155
Mbps ATM networks.
The IDT77V252 is fabricated using state-of-the-art CMOS
technology, providing the highest levels of integration, perfor-
mance and reliability, with the low-power consumption char-
acteristics of CMOS.
T ra nsm it
C o n tro l
Tx
U to p ia
In terface
8
/
T x U to p ia
Bus
32
S R A M IN T E R F A C E
/
SRAM
Bus
PCI Bus
.
32
/
PC I
In terface
Rx
U top ia
Interface
8
Receive
C o n tro l
8
/
R x U to p ia
Bus
/
U tilit y
EE PR O M O U T
E E P R O M IN
5 3 5 0 d rw 0 2
Block Diagram of the 77V252 ABR SAR
2
IDT77V252 155Mb/s ATM Segmentation & Reassembly (SAR) Controller
with ABR for the PCI Local Bus
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
PACKAGE PINOUT
GND
Vcc
R EQ
G NT
CLK
R ST
GND
TEST[0]
TEST[1]
HS_H AN D LE
CLK_OUT
Vcc
Vcc
NC
HS_EN U M
H S_LED
UTOPIA_MODE
TXPARITY
PHY_CLK
RXCLK
GND
RX_CTRL_IN
RX_CTRL_OUT
RXSOC
RXDATA(7)
RXDATA(6)
RXDATA(5)
RXDATA(4)
GND
RXDATA(3)
RXDATA(2)
RXDATA(1)
RXDATA(0)
GND
TXCLK
TX_CTRL_IN
TX_CTRL_OUT
TXSOC
GND
TXDATA(7)
TXDATA(6)
VCC
TXDATA(5)
TXDATA(4)
GND
TXDATA(3)
TXDATA(2)
TXDATA(1)
TXDATA(0)
1)
U TL_C S(
UTL_CS(
0)
Vcc
Vcc
AD(31)
AD(30)
AD(29)
AD(28)
AD(27)
AD(26)
GND
GND
AD(25)
AD(24)
C/BE(3)
IDSEL
AD(23)
AD(22)
GND
GND
AD(21)
Vcc
AD(20)
AD(19)
AD(18)
AD(17)
AD(16)
GND
GND
C/BE(2)
Vcc
FRAM E
I
RDY
TRDY
DEVSEL
STO P
GND
GND
I TA
N
Vcc
PERR
SERR
PAR
C/BE(1)
AD(15)
GND
GND
AD(14)
AD(13)
AD(12)
AD(11)
AD(10)
AD(9)
AD(8)
GND
208 2 2 2 2 2
00000
1
76543
2
Index
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52 5 5 5 5 5 5
345678
2221111111111111111111111111111111111111111111
0009999999999888888888877777777776666666666555
2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
IDT77V252 SAR Controller
135
With ABR Support
134
133
208 Pin PQFP
132
Pinout
131
130
PU-208
129
128
127
Refer to PSC-4053 for
126
detailed package drawing
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
1 1 1 1 1 106
5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 0 0 0 0 0 105
9 01 23 4 567 8 9 012 3 456 789 0 1 234 5 678 9 01 2 345 6 78 901 2 34
GND
PHY_I
NT
PHY_R ST
UTL_ALE
UTL_RD
UTL_W R
GND
UTL_AD(7)
UTL_AD(6)
UTL_AD(5)
UTL_AD(4)
Vcc
UTL_AD(3)
GND
UTL_AD(2)
UTL_AD(1)
UTL_AD(0)
Vcc
SAR_CLK
GND
EEDO
EEDI
EESCLK
EECS
Vcc
E_CE
SR_I/O(31)
SR_I/O(30)
SR_I/O(29)
GND
SR_I/O(28)
SR_I/O(27)
SR_I/O(26)
SR_I/O(25)
SR_I/O(24)
Vcc
SR_I/O(23)
GND
SR_I/O(22)
SR_I/O(21)
SR_I/O(20)
SR_I/O(19)
SR_I/O(18)
SR_I/O(17)
GND
SR_I/O(16)
SR_I/O(15)
SR_I/O(14)
SR_I/O(13)
SR_I/O(12)
SR_I/O(11)
Vcc
Vcc
GND
C/BE(0)
AD(7)
Vcc
AD(6)
AD(5)
AD(4)
GND
SR_A17
AD(3)
AD(2)
AD(1)
AD(0)
GND
SR_A15
SR_W E
SR_A13
SR_A8
SR_A9
SR_A11
SR _O E
SR_A10
SR _C S
SR_A16
GND
SR_A14
Vcc
SR_A12
SR_A7
SR_A6
SR_A5
SR_A4
SR_A3
SR_A2
SR_A1
SR_A0
SR_A18
GND
SR_I/O(0)
SR_I/O(1)
SR_I/O(2)
SR_I/O(3)
SR_I/O(4)
SR_I/O(5)
GND
SR_I/O(6)
SR_I/O(7)
SR_I/O(8)
SR_I/O(9)
SR_I/O(10)
GND
5350 drw 03
3
IDT77V252 155Mb/s ATM Segmentation & Reassembly (SAR) Controller
with ABR for the PCI Local Bus
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
PACKAGE DRAWING
1.228 ±0.016 (31.2 ±0.4)
1.10 ±0.004 (28.0 ±0.1)
208
157
1
0.02 ±0.004
(0.5 ±0.1)
Index
156
0.008 ±0.004
(0.2 ±0.1)
52
105
53
104
0.133 ±0.004
(3.37 ±0.1)
0.013 ±0.002
(0.33 ±0.06)
0.024 ±0.008
(0.6 ±0.2)
0.063 (1.6)
5350 drw 04
1.10 ±0.004 (28.0 ±0.1)
1.228 ±0.016 (31.2 ±0.4)
4
IDT77V252 155Mb/s ATM Segmentation & Reassembly (SAR) Controller
with ABR for the PCI Local Bus
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
PIN DEFINITIONS
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
V
CC
A D (31)
A D (30)
A D (29)
A D (28)
A D (27)
A D (26)
GND
GND
A D (25)
A D (24)
C /BE(3)
ID S E L
A D (23)
A D (22)
GND
GND
A D (21)
V
CC
A D (20)
A D (19)
A D (18)
A D (17)
A D (16)
GND
GND
C /BE(2)
V
CC
.rame
IRDY
TRDY
DEVSEL
STOP
GND
GND
INTA
V
CC
PERR
SERR
PAR
C /BE(1)
A D (15)
GND
GND
A D (14)
A D (13)
A D (12)
A D (11)
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I/O
I/O
I
I/O
I/O
I
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I
O
I
I/O
O
I/O
I/O
I/O
I
I
I/O
I/O
I/O
I/O
Bus Name
pow er
PCI
PCI
PCI
PCI
PCI
PCI
pow er
pow er
PCI
PCI
PCI
PCI
PCI
PCI
pow er
pow er
PCI
pow er
PCI
PCI
PCI
PCI
PCI
pow er
pow er
PCI
pow er
PCI
PCI
PCI
PCI
PCI
pow er
pow er
PCI
pow er
PCI
PCI
PCI
PCI
PCI
pow er
pow er
PCI
PCI
PCI
PCI
address/data line
address/data line
address/data line
address/data line
5350 tbl 01
Description
address/data line
address/data line
address/data line
address/data line
address/data line
address/data line
address/data line
address/data line
bus com m and
bus ID select
address/data line
address/data line
address/data line
address/data line
address/data line
address/data line
address/data line
address/data line
bus com m and
cy cle fram e
initiator ready
target ready
target ind icating address decode
target req uesting m aster to stop
"interrupt" "A " "request"
data parity error
sy stem error
parity (for A D [0:31] and C/B E[0:3])
bus com m and
address/data line
5
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