video overlay systems. The device accepts the horizontal
sync (HSYNC) signal as the input reference clock, and
generates a frequency-locked high speed output.
Stored in the device are the multipliers for 16
combinations of popular frequencies for analog and
digital TV and set-top box systems. Frequency-locked
outputs include 1X, 4X, and 8X the subcarrier
frequencies of NTSC and PAL systems, and 27MHz plus
13.5MHz for digital video systems. In most selections,
the chip recovers the HSYNC clock by outputting a low
jitter 50% duty cycle version of HSYNC. Also available is
an inverted recovered HSYNC clock, and a double speed
recovered HSYNC clock.
ICS can customize this device for any other different
frequencies.
Features
• Packaged in 16 pin narrow (150 mil) SOIC
• Exact ratios stored in the device eliminate the need
for external dividers
• Accepts HSYNC of 15.625kHz or 15.73426kHz
• Highly accurate frequency generation within 1 ppm
• Generates NTSC/PAL subcarrier frequencies, and
4X and 8X of those frequencies
• Generates 27MHz and 13.5MHz
• 2X HSYNC clock available
• Recovered HSYNC clock available
• Inverted HSYNC clock available
• 3.3V operation
Block Diagram
VDD
2
GND
2
CAP1
CAP2
Output
Buffer
4
CLK1
CLK2
CLK3
FS0-3
HSYNC
Input Clock
Input
Buffer
Clock
Synthesis
and
Control
Circuitry
Output
Buffer
Output
Buffer
OE (all outputs)
1
111301
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com
MDS1573-03 A
MK1573-03
GenClock™ HSYNC to Video Clock
Pin Assignment
Output Clocks Decoding Table MK1573-03 (MHz)
HSYNC
VDD
VDD
CAP1
GND
CAP2
GND
FS0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FS3
N/C
FS2
FS1
CLK2
OE
CLK1
CLK3
Decode
Address
HSYNC
FS3:0
(Hex)
pin 1
0
15.625k
0000
1
15.734264k
0001
2
15.625k
0010
3
15.734264k
0011
4
15.625k
0100
5
15.734264k
0101
6
15.625k
0110
7
15.734264k
0111
8
15.625k
1000
9
15.734264k
1001
A
15.625k
1010
B
15.734264k
1011
C
15.625k
1100
D
15.734264k
1101
E
15.734264k
1110
F
15.625k
1111
Multiplier
On-chip
2270
1820
1728
1716
960
953 1/3
3840
3840
2270
1820
2270
1820
2048
808
1218
1260
CLK 1
pin 10
35.46875M
28.63636M
27M
27M
15M
15M
60M
60.41957M
35.46875M
28.63636M
35.46875M
28.63636M
32M
12.71329M
19.164M
19.6875M
CLK 2
pin 12
15.62k
15.734264k
13.5M
13.5M
7.5M
7.5M
30M
30.20979M
17.734375M
14.31818M
15.625k
15.734264k
16M
15.734264k
Off
Off
CLK 3
pin 9
31.25k
31.4685k
15.625k
15.734264k
15.625k
15.734264k
15.625k
15.734264k
4.433594M
3.579545M
15.625k
15.734264k
15.625k
31.4685k
Off
Off
16 pin (150 mil) SOIC
• 0 = connect directly to ground, 1 = connect directly to VDD.
• CLK2 is a recovered HSYNC (with 50% duty cycle) on selections in italic.
• HSYNC reference outputs on CLK3 (in italic) are inverted, recovered HSYNC.
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
HSYNC
VDD
VDD
CAP1
GND
CAP2
GND
FS0
CLK3
CLK1
OE
CLK2
FS1
FS2
N/C
FS3
Type Description
I
P
P
I
P
I
P
I
O
O
I
O
I
I
-
I
HSYNC clock input. The output clocks are synchronized to the HSYNC falling edge.
Connect to +3.3V.
Connect to +3.3V.
Connect a 0.047µF ceramic NP0 capacitor and a 22kΩ resistor in series and also a parallel .0022µF low leakage capacitor between this pin and CAP2.
Connect to ground.
Connect a 0.047µF ceramic NP0 capacitor and a 22kΩ resistor in series and also a parallel .0022µF low leakage capacitor between this pin and CAP1.
Connect to ground.
Frequency Select 0. Determines CLK outputs (with given input) per table above.
Clock 3 determined by status of FS3:0 per table above.
Clock 1 determined by status of FS3:0 per table above.
Output Enable. Tri-states the three output clocks when low.
Clock 2 determined by status of FS3:0 per table above.
Frequency Select 1. Determines CLK outputs (with given input) per table above.
Frequency Select 2. Determines CLK outputs (with given input) per table above.
No connect. Nothing is connected to this pin.
Frequency Select 3. Determines CLK outputs (with given input) per table above.
Type: I = Input, O = output, P = power supply connection
2
111301
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com
MDS1573-03 A
MK1573-03
GenClock™ HSYNC to Video Clock
External Components/Crystal Selection
The MK1573 requires a minimum number of external components for proper operation. A 0.047µF capacitor should
be connected in series with a 22kΩ resistor between CAP1 and CAP2 pin (resistor on CAP2 side), with a parallel low
leakage 0.0022µF capacitor between CAP1 and CAP2 pins. A decoupling capacitor of 0.1µF must be connected
between VDD and GND pins (pins 2 and 3, 5 and 7) close to the chip, and 33Ω terminating resistors can be used on
clock outputs with traces longer than 1 inch.
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage Temperature
Max of 10 seconds
-65
3.15
2
0.8
IOH=-4mA
IOH=-25mA
IOL=25mA
No Load, VDD=5.0V
Each output
Any clock selection
10
±100
5
0
15.734264
15.625
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
40
0.7
0.7
49 to 51
±200
±1.5
50
3
1.5
1.5
60
1
VDD-0.4
2.4
0.4
Referenced to GND
-0.5
0
Minimum
Typical
Maximum
7
VDD+0.5
70
250
150
3.45
Units
V
V
°C
°C
°C
V
V
V
V
V
V
mA
mA
pF
ppm
kHz
kHz
ns
ns
%
ps
ns
ns
µs
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage
Output High Voltage
Output Low Voltage
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance
Actual mean frequency error versus target, note 2
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Frequency, NTSC
Input Frequency, PAL
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle, High Time
Absolute Clock Period Jitter, MHz outputs
Absolute Clock Period Jitter, kHz outputs
Output Enable Time, OE high to outputs on
Output Disable Time, OE low to tri-state
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Most selections have zero ppm error. Some selections have a maximum of 1 ppm synthesis error.
3
111301
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com
MDS1573-03 A
MK1573-03
GenClock™ HSYNC to Video Clock
Clock Waveforms
In addition to generating the video clock on CLK1 (pin 10), the MK1573 also outputs the recovered HSYNC
clocks. On certain selections, a double speed recovered HSYNC clock is also available. These recovered clocks
will have lower jitter than the HSYNC input due to the filtering action of the PLL. The jitter spectrum of the
recovered clocks will be reduced at frequencies higher than the loop bandwidth. The waveforms of the recovered
clocks fall into one of three different groups depending on the address selection:
Addresses 2 to 7 and C
HSYNC
input
CLK3
Addresses A and B
HSYNC
input
CLK2
CLK3
Addresses D, E, and F
HSYNC
input
CLK2
CLK3
The recovered clocks are triggered by the falling edge of HSYNC and are delayed by about 100ns.
4
111301
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com
MDS1573-03 A
MK1573-03
GenClock™ HSYNC to Video Clock
Package Outline and Package Dimensions
16 pin SOIC narrow
Inches
Symbol Min
Max
A
0.055 0.070
b
0.013 0.019
c
0.007 0.010
D
0.385 0.400
E
0.150 0.160
H
0.225 0.245
e
.050 BSC
h
0.016
Q
0.004 0.01
Millimeters
Min
Max
1.397 1.778
0.330 0.483
0.191 0.254
9.779 10.160
3.810 4.064
5.715 6.223
1.27 BSC
0.406
0.102 0.254
E
H
D
h x 45°
Q
c
e
b
A
Ordering Information
Part/Order Number
MK1573-03S
MK1573-03STR
Marking
MK1573-03S
MK1573-03S
Package
16 pin narrow SOIC
Add Tape & Reel
Temperature
0-70°C
0-70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied.
This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high
reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change
any circuitry or specifications without notice. MicroClock does not authorize or warrant any ICS product for use in life support devices or critical medical
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