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CY7C1354C-200BGIT: 产品描述ZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA119, (14 X 22 X 2.4) MM, PLASTIC, BGA-119; 产品类别存储存储; 文件大小507KB，共28页; 制造商Cypress(赛普拉斯)

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CY7C1354C-200BGIT概述

ZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA119, (14 X 22 X 2.4) MM, PLASTIC, BGA-119

CY7C1354C-200BGIT规格参数

参数名称	属性值
厂商名称	Cypress(赛普拉斯)
零件包装代码	BGA
包装说明	(14 X 22 X 2.4) MM, PLASTIC, BGA-119
针数	119
Reach Compliance Code	unknown
ECCN代码	3A991.B.2.A
最长访问时间	3.2 ns
其他特性	PIPELINED ARCHITECTURE
JESD-30 代码	R-PBGA-B119
JESD-609代码	e0
长度	22 mm
内存密度	9437184 bit
内存集成电路类型	ZBT SRAM
内存宽度	36
功能数量	1
端子数量	119
字数	262144 words
字数代码	256000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	256KX36
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY
并行/串行	PARALLEL
认证状态	Not Qualified
座面最大高度	2.4 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3.135 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	TIN LEAD
端子形式	BALL
端子节距	1.27 mm
端子位置	BOTTOM
宽度	14 mm
Base Number Matches	1

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CY7C1354C

CY7C1356C

9-Mbit (256K x 36/512K x 18)

Pipelined SRAM with NoBL™ Architecture

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 200, and 166 MHz

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 3.3V power supply (V

)

• 3.3V or 2.5V I/O power supply (V

DDQ

)

• Fast clock-to-output times

— 2.8 ns (for 250-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Available in lead-free 100-Pin TQFP package, lead-free

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

•

Burst capability–linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

[1]

The CY7C1354C and CY7C1356C are 3.3V, 256K x 36 and

512K x 18 Synchronous pipelined burst SRAMs with No Bus

Latency™ (NoBL™) logic, respectively. They are designed to

support unlimited true back-to-back Read/Write operations

with no wait states. The CY7C1354C and CY7C1356C are

equipped with the advanced (NoBL) logic required to enable

consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data in systems that require frequent

Write/Read transitions. The CY7C1354C and CY7C1356C are

pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the Byte Write Selects

(BW

–BW

for CY7C1354C and BW

–BW

for CY7C1356C)

and a Write Enable (WE) input. All writes are conducted with

on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Logic Block Diagram–CY7C1354C (256K x 36)

A0, A1, A

MODE

CLK

CEN

ADDRESS

A1'

A0'

BURST

LOGIC

ADV/LD

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

WRITE

DRIVERS

MEMORY

ARRAY

DQs

DQP

INPUT

CE1

CE2

CE3

READ LOGIC

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note

System Design Guidelines

on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05538 Rev. *G

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised September 14, 2006

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CY7C1354C-200BGIT相似产品对比

	CY7C1354C-200BGIT	CY7C1356C-200AXCT	CY7C1354C-200BGCT	CY7C1354C-250AXCT	CY7C1356C-166BGCT	CY7C1356C-166BZXC
描述	ZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA119, (14 X 22 X 2.4) MM, PLASTIC, BGA-119	ZBT SRAM, 512KX18, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	ZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA119, (14 X 22 X 2.4) MM, PLASTIC, BGA-119	ZBT SRAM, 256KX36, 2.8ns, CMOS, PQFP100, (14 X 20 X 1.4) MM, LEAD FREE, PLASTIC, TQFP-100	ZBT SRAM, 512KX18, 3.5ns, CMOS, PBGA119, (14 X 22 X 2.4) MM, PLASTIC, BGA-119	ZBT SRAM, 512KX18, 3.5ns, CMOS, PBGA165, (13 X 15 X 1.4) MM, LEAD FREE, PLASTIC, FBGA-165
厂商名称	Cypress(赛普拉斯)	-	-	Cypress(赛普拉斯)	Cypress(赛普拉斯)	Cypress(赛普拉斯)
零件包装代码	BGA	QFP	BGA	QFP	BGA	BGA
包装说明	(14 X 22 X 2.4) MM, PLASTIC, BGA-119	LQFP,	(14 X 22 X 2.4) MM, PLASTIC, BGA-119	LQFP,	(14 X 22 X 2.4) MM, PLASTIC, BGA-119	(13 X 15 X 1.4) MM, LEAD FREE, PLASTIC, FBGA-165
针数	119	100	119	100	119	165
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	3.2 ns	3.2 ns	3.2 ns	2.8 ns	3.5 ns	3.5 ns
其他特性	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 代码	R-PBGA-B119	R-PQFP-G100	R-PBGA-B119	R-PQFP-G100	R-PBGA-B119	R-PBGA-B165
JESD-609代码	e0	e0	e0	e3/e4	e0	e1
长度	22 mm	20 mm	22 mm	20 mm	22 mm	15 mm
内存密度	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit
内存集成电路类型	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM
内存宽度	36	18	36	36	18	18
功能数量	1	1	1	1	1	1
端子数量	119	100	119	100	119	165
字数	262144 words	524288 words	262144 words	262144 words	524288 words	524288 words
字数代码	256000	512000	256000	256000	512000	512000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	256KX36	512KX18	256KX36	256KX36	512KX18	512KX18
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	BGA	LQFP	BGA	LQFP	BGA	LBGA
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY	FLATPACK, LOW PROFILE	GRID ARRAY	FLATPACK, LOW PROFILE	GRID ARRAY	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	2.4 mm	1.6 mm	2.4 mm	1.6 mm	2.4 mm	1.4 mm
最大供电电压 (Vsup)	3.6 V	3.63 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	TIN LEAD	TIN LEAD	TIN LEAD	MATTE TIN/NICKEL PALLADIUM GOLD	TIN LEAD	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL	GULL WING	BALL	GULL WING	BALL	BALL
端子节距	1.27 mm	0.65 mm	1.27 mm	0.65 mm	1.27 mm	1 mm
端子位置	BOTTOM	QUAD	BOTTOM	QUAD	BOTTOM	BOTTOM
宽度	14 mm	14 mm	14 mm	14 mm	14 mm	13 mm

CY7C1354C-200BGIT

CY7C1354C-200BGIT概述

CY7C1354C-200BGIT规格参数

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