Not Recommended for New Design,
Replace with CAT24C128
CAT24AC128
128kbit I
2
C Serial CMOS EEPROM With Three Chip Address Input Pins
FEATURES
I
400kHz (2.5V) and 100kHz (1.8V) I
2
C bus
I
Commercial, industrial and extended
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
compatibility
I
1.8 to 5.5 volt operation
I
Low power CMOS technology
I
Schmitt trigger filtered inputs for noise
automotive temperature ranges
I
Write protect feature
– Entire array protected when WP at V
IH
I
1,000,000 program/erase cycles
I
100 year data retention
I
8-Pin DIP, 8-Pin SOIC (JEDEC/EIAJ) or
suppression
I
64-Byte page write buffer
I
Self-timed write cycle with auto-clear
14-pin TSSOP
DESCRIPTION
The CAT24AC128 is a 128kbit Serial CMOS EEPROM
internally organized as 16,384 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24AC128
features a 64-byte page write buffer. The device operates
via the I
2
C bus serial interface and is available in 8-pin
DIP, 8-pin SOIC or 14-pin TSSOP packages. Three
device address inputs allows up to 8 devices to share a
common 2-wire I
2
C bus.
PIN CONFIGURATION
DIP Package (P, L)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
BLOCK DIAGRAM
EXTERNAL LOAD
SOIC Package (J, K, W, X)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
512
SDA
START/STOP
LOGIC
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
TSSOP Package (U14, Y14)
A0
A1
NC
NC
NC
A2
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V CC
WP
NC
NC
NC
SCL
SDA
XDEC
WP
CONTROL
LOGIC
256
E
2
PROM
256X512
PIN FUNCTIONS
Pin Name
SDA
SCL
WP
V
CC
V
SS
A0 - A2
Function
Serial Data/Address
Serial Clock
Write Protect
+1.8V to +5.5V Power Supply
Ground
Device Address Inputs
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
HIGH VOLTAGE/
TIMING CONTROL
DATA IN STORAGE
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1028, Rev. J
CAT24AC128
Not Recommended
for New Design,
Replace with CAT24C128
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
Typ.
Max.
Units
Cycles/Byte
Years
Volts
mA
1,000,000
100
2000
100
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current - Read
Power Supply Current - Write
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= +3.0V)
Output Low Voltage (V
CC
= +1.8V)
I
OL
= 3.0 mA
I
OL
= 1.5 mA
Test Conditions
f
SCL
= 100 KHz
V
CC
= 5V
f
SCL
= 100 KHz
V
CC
= 5V
V
IN
= GND or V
CC
V
CC
= 5V
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
–1
V
CC
x 0.7
Min
Typ
Max
1
3
1
3
3
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
Units
mA
mA
µA
µA
µA
V
V
V
V
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
Test
C
I/O(3)
C
IN(3)
Input/Output Capacitance (SDA)
Input Capacitance (SCL, WP, A0, A1, A2)
Conditions
V
I/O
= 0V
V
IN
= 0V
Min
Typ
Max
8
6
Units
pF
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10µA for the Extended Automotive temperature range.
Doc. No. 1028, Rev. J
2
Not Recommended for New Design,
Replace with CAT24C128
A.C. CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
V
CC
= 1.8 V - 5.5 V
Min
F
SCL
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
t
WR
t
SP
Clock Frequency
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
Input Suppression (SDA, SCL)
4.7
100
5
100
0.1
4.7
4.0
4.7
4.0
4.0
0
100
1.0
300
0.6
50
Max
100
3.5
0.05
1.2
0.6
1.2
0.6
0.6
0
100
CAT24AC128
V
CC
= 2.5 V - 5.5 V
Min
Max
400
0.9
Units
kHz
µs
µs
µs
µs
µs
µs
ns
ns
0.3
300
µs
ns
µs
ns
5
100
ms
ns
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During
the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
address.
FUNCTIONAL DESCRIPTION
The CAT24AC128 supports the I
2
C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24AC128
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or receiver,
but the Master device controls which mode is activated.
3
Doc. No. 1028, Rev. J
CAT24AC128
Not Recommended
for New Design,
Replace with CAT24C128
I
2
C BUS PROTOCOL
The features of the I
2
C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24AC128 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
tR
tLOW
PIN DESCRIPTIONS
SCL:
Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA:
Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
WP:
Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
A0, A1, A2:
Device Address Inputs
These inputs set the device address when cascading
multiple devices. When these pins are left floating the
default values are zeroes. A maximum of eight devices
can be cascaded.
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STO
SDA IN
tAA
SDA OUT
tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. 1028, Rev. J
4
Not Recommended for New Design,
Replace with CAT24C128
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The next three significant bits (A2, A1, A0)
are the device address bits and define which device the
master is accessing. Up to eight CAT24AC128 devices
may be individually addressed by the system. The last
bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24AC128 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24AC128 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT24AC128 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
CAT24AC128
When the CAT24AC128 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24AC128 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24AC128. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24AC128 acknowledges once
more and the Master generates the STOP condition. At
this time, the device begins an internal programming
cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24AC128 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
*A0, A1 and A2 must compare to its corresonding hard wired inputs (pins 1, 2 and 3).
5
Doc. No. 1028, Rev. J
DSP 与 ARM 处理器
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