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SN74ALVC7813
64
×
18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS594A – OCTOBER 1997 – REVISED APRIL 1998
D
D
D
D
D
D
D
D
D
D
D
D
D
Member of the Texas Instruments
Widebus™ Family
Low-Power Advanced CMOS Technology
Operates From 3-V to 3.6-V V
CC
Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident
Read and Write Operations Synchronized
to Independent System Clocks
Half-Full Flag and Programmable
Almost-Full/Almost-Empty Flag
Bidirectional Configuration and Width
Expansion Without Additional Logic
Input-Ready Flag Synchronized to Write
Clock
Output-Ready Flag Synchronized to Read
Clock
Fast Access Times of 13 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
Data Rates up to 50 MHz
Pin-to-Pin Compatible With SN74ACT7803,
SN74ACT7805, and SN74ACT7813
Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Lead Spacing
DL PACKAGE
(TOP VIEW)
description
The SN74ALVC7813 is suited for buffering
asynchronous data paths up to 50-MHz clock
rates and 13-ns access times. This device is
designed for 3-V to 3.6-V V
CC
operation. Two
devices can be configured for bidirectional data
buffering without additional logic.
RESET
D17
D16
D15
D14
D13
D12
D11
D10
V
CC
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
HF
PEN
AF/AE
WRTCLK
WRTEN2
WRTEN1
IR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OE1
Q17
Q16
Q15
GND
Q14
V
CC
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
V
CC
Q4
Q3
Q2
GND
Q1
Q0
RDCLK
RDEN
OE2
OR
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.
Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input
ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low
and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,
regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output
buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET) must be asserted while at
least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO
initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO
must be reset upon power up.
The SN74ALVC7813 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1998, Texas Instruments Incorporated
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•
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1
SN74ALVC7813
64
×
18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS594A – OCTOBER 1997 – REVISED APRIL 1998
logic symbol
†
Φ
FIFO 64
×
18
RESET
WRTCLK
&
WRTEN
RDCLK
&
EN1
In Ready
Half-Full
Almost-Full/Empty
Out Ready
28
22
24
29
IR
HF
AF/AE
OR
1
RESET
WRTCLK
WRTEN1
WRTEN2
RDCLK
OE1
OE2
32
56
30
25
27
26
&
RDEN
31
RDEN
PEN
23
Program Enable
33
34
36
37
38
40
41
42
43
Data
Data
1
45
46
47
48
49
51
53
54
17
17
55
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
21
20
19
18
17
16
15
14
12
11
9
8
7
6
5
4
3
2
0
0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303
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SN74ALVC7813
64
×
18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS594A – OCTOBER 1997 – REVISED APRIL 1998
functional block diagram
OE1
OE2
D0–D17
Output
Control
RDCLK
RDEN
Synchronous
Read
Control
RAM
Read
Pointer
64
×
18
WRTCLK
WRTEN1
WRTEN2
Synchronous
Write
Control
Write
Pointer
Register
Q0–Q17
RESET
PEN
Reset
Logic
Status-
Flag
Logic
OR
IR
HF
AF/AE
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DALLAS, TEXAS 75265
3
SN74ALVC7813
64
×
18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS594A – OCTOBER 1997 – REVISED APRIL 1998
Terminal Functions
TERMINAL
NAME
AF/AE
NO.
24
2–9, 11–12,
14–21
22
28
I/O
DESCRIPTION
Almost-full/almost-empty flag. Depth-offset values can be programmed for this flag, or the default
value of 8 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high
when memory contains X or fewer words or (64 – Y) or more words. AF/AE is high after reset.
18-bit data input port
Half-full flag. HF is high when the FIFO memory contains 32 or more words. HF is low after reset.
Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO
is full and writes are disabled. IR is low during reset and goes high on the second low-to-high transition
of WRTCLK after reset.
Output enables. When OE1, OE2, and RDEN are low and OR is high, data is read from the FIFO on
a low-to-high transition of RDCLK. When either OE1 or OE2 is high, reads are disabled and the data
outputs are in the high-impedance state.
Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the
FIFO is empty and reads are disabled. Ready data is present on Q0–Q17 when OR is high. OR is low
during reset and goes high on the third low-to-high transition of RDCLK after the first word is loaded
to empty memory.
Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D7
is latched as an AF/AE offset value when PEN is low and WRTCLK is high.
18-bit data output port. After the first valid write to empty memory, the first word is output on Q0–Q17
on the third rising edge of RDCLK. OR also is asserted high at this time to indicate ready data. When
OR is low, the last word read from the FIFO is present on Q0–Q17.
Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A
low-to-high transition of RDCLK reads data from memory when OE1, OE2, and RDEN are low and OR
is high. OR is synchronous to the low-to-high transition or RDCLK.
Read enable. When RDEN, OE1, and OE2 are low and OR is high, data is read from the FIFO on the
low-to-high transition of RDCLK.
Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of
WRTCLK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high.
Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A
low-to-high transition of WRTCLK writes data to memory when WRTEN2 is low, WRTEN1 is high, and
IR is high. IR is synchronous to the low-to-high transition of WRTCLK.
Write enables. When WRTEN1 is high, WRTEN2 is low, and IR is high, data is written to the FIFO on
a low-to-high transition of WRTCLK.
O
D0–D17
HF
IR
I
O
O
OE1
OE2
56
30
I
OR
29
O
PEN
23
33–34, 36–38,
40–43, 45–49,
51, 53–55
32
I
Q0–Q17
O
RDCLK
I
RDEN
RESET
31
1
I
I
WRTCLK
WRTEN1
WRTEN2
25
27
26
I
I
4
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