S i3 2 1 7 2 / 3 / 5
P
R O
S L I C
®
S
I N G L E
-C
H I P
FXS S
O L U T I O N W I T H
I
N T E G R A T E D
S
E R I A L
I
N T E R F A C E
(I SI )
Si32172/3/5 Features
Complete FXS solution in 5 x 7 mm
3-wire ISI combines PCM, SPI, and
interrupt data
Performs all BORSCHT functions
Ideal for short to medium loops
Global programmability
Internal balanced or unbalanced
ringing
Patented low power ringing
Simplified configuration and
diagnostics
Supported by ProSLIC API
Ultra low power consumption
Integrated tracking dc-dc controller
with direct connection to MOSFET
Wideband voice support
(Si32172/3)
On-hook transmission
Loop or ground start operation
Smooth polarity reversal
A-Law/μ-Law companding,
linear PCM
Software-programmable
parameters:
Ringing
frequency, amplitude,
cadence, and waveshape
Two-wire ac impedance
Transhybrid balance
DC current loop feed (10-45 mA)
Loop closure and ring trip
thresholds
Ground key detect threshold
Ordering Information
See page 37.
DTMF generation
DTMF detection (Si32175)
Pulse metering
3.3 V operation
Support for 1.8 V I/O
Maximum battery up to –140 V
Pb-free/RoHS-compliant
packaging
Pin Assignments
Si32172/3/5
Applications
Customer Premise Equipment
(CPE)
VoIP DSL Gateways and Routers
Wireless Local Loop (WLL)
Integrated Access Devices (IAD)
Analog Terminal Adapters (ATA)
Small Office/Home Office PBX
Patents pending
Description
T
he Si32172/3/5 devices are pin-compatible single-channel ProSLIC products that
implement a complete foreign exchange station (FXS) telephony interface solution in
accordance with all relevant LSSGR, ITU, and ETSI specifications. The Si32172/3/5
ProSLIC ICs operate from a 3.3 V supply and use Silicon Labs’ proprietary three-
wire digital Integrated Serial Interface (ISI) with 3.3 V or 1.8 V I/O to connect to SoCs
with the ISI pre-integrated. The Si32172/3/5 integrated dc-dc controller automatically
generates the optimal battery voltages required for each linestate. Si32172/3/5 ICs
are available with voltage ratings of –110 V or –140 V to support a wide range of
ringing voltages. See the Ordering Guide for the voltage rating of each Si32172/3/5
version. The Si32172/3/5 devices are available in a 5x7 mm 42-pin QFN package.
Rev. 1.0 5/13
Copyright © 2013 by Silicon Laboratories
Si32172/3/5
Si32172/3/5
Functional Block Diagram
2
Rev. 1.0
Si32 172 /3/5
T
A B L E
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. FXS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.1. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.2. Linefeed Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.3. Line Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.1. Thermal Overload Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.2. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.3. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.4. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.5. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.6. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.7. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.8. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.9. DTMF Detection (Si32175 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.10. Pulse Metering (Si32175 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.11. DC-DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.12. Wideband Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.13. In-Circuit and Metallic Loop Testing (MLT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
7. System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
7.1. Integrated Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
7.2. Input/Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
8. Pin Descriptions: Si32172/3/5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
10. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
11. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
11.1. 42-Pin QFN/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
12. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
12.1. QFN PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
12.2. QFN Solder Mask Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
12.3. QFN Stencil Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
12.4. QFN Card Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
13. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
13.1. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
13.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Rev. 1.0
3
Si32172/3/5
1. Electrical Specifications
Table 1. Recommended Operating Conditions
1
Parameter
Ambient Temperature
Silicon Junction Temperature,
QFN-42
Supply Voltage, Si32172/3/5
Battery Voltage, Si32172/5
2
Battery Voltage, Si32173
2
3.3 V IO Supply Voltage
1.8 V IO Supply Voltage
Symbol
T
A
T
JHV
V
DD
V
BAT
V
BAT
V
DDIO
V
DDIO
Test Condition
F-grade
G-grade
Linefeed Die
Min*
0
–40
—
3.13
–110
–140
3.13
1.71
Typ
25
25
—
3.3
–95
–130
3.3
1.8
Max*
70
85
145
3.47
–15
–15
3.47
1.89
Unit
°C
°C
°C
V
V
V
V
V
Notes:
1.
All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at
nominal supply voltages and an operating temperature of 25
°
C unless otherwise stated.
2.
Operation at minimum voltage dependent upon loop conditions and dc-dc converter configuration.
Table 2. Power Supply Characteristics
T
A
= 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted.
Parameter
Supply Currents:
Reset
Supply Currents:
High Impedance,
Open
Supply Currents:
Forward/Reverse,
On-hook
Supply Currents:
Forward/Reverse,
On-hook
Supply Currents:
Tip/Ring Open,
On-hook
Symbol
I
DD
I
VBAT
I
DD
I
VBAT
I
DD
I
VBAT
I
DD
I
VBAT
I
DD
I
VBAT
Test Condition
V
T
and V
R
= Hi-Z , RST = 0
Min
—
—
Typ
6.3
0
20.8
0.6
10.8
0.6
31.2
2.1
10.9
0.4
Max
—
—
—
—
—
—
—
—
—
—
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
T
and V
R
= Hi-Z
—
—
V
TR
= –48 V,
Automatic Power Save Mode enabled
V
TR
= –48 V,
Automatic Power Save Mode disabled
V
T
or V
R
= –48 V
V
R
or V
T
= Hi-Z,
Automatic Power Save Mode enabled
—
—
—
—
—
—
Notes:
1.
All specifications are for a single channel of Si3217x with a tracking flyback dc-dc converter.
2.
I
LOOP
is the dc current in the subscriber loop during the off-hook state.
4
Rev. 1.0
Si32 172 /3/5
Table 2. Power Supply Characteristics (Continued)
T
A
= 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted.
Parameter
Supply Currents:
Tip/Ring Open,
On-hook
Supply Currents:
Forward/Reverse OHT,
On-hook
Supply Currents:
Forward/Reverse Active,
Off-hook
Supply Currents:
Ringing
Symbol
I
DD
Test Condition
V
T
or V
R
= –48 V
V
R
or V
T
= Hi-Z,
Automatic Power Save Mode disabled
V
TR
=48 V,
Min
—
Typ
30.6
Max
—
Unit
mA
I
VBAT
I
DD
I
VBAT
I
DD
I
VBAT
I
DD
I
VBAT
V
TR
=55V
RMS
+ 0 V
DC
,
balanced, sinusoidal, f = 20 Hz,
RLOAD = 5 REN = 1400
Ω
I
LOOP
= 20 mA R
LOAD
= 200
Ω,
—
—
—
—
—
—
—
1.3
43.8
2.9
44.6
21.3
35.8
37.5
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
Notes:
1.
All specifications are for a single channel of Si3217x with a tracking flyback dc-dc converter.
2.
I
LOOP
is the dc current in the subscriber loop during the off-hook state.
Table 3. AC Characteristics for FXS
T
A
= 0 to 70 °C (F grade) or –40 to +85 °C (G grade) unless otherwise noted.
Parameter
Overload Level
Overload Compression
Single Frequency Distortion
1
Test Condition
TX/RX Performance
Min
2.5
Typ
—
—
—
—
Max
—
—
–40
–63
Unit
V
PK
dB
dB
2-Wire – PCM
2-Wire – PCM or PCM – 2-Wire:
200 Hz to 3.4 kHz
PCM – 2-Wire – PCM:
200 Hz – 3.4 kHz,
16-bit Linear mode
Figure 3
—
—
Signal-to-(Noise + Distortion)
Ratio
2
200 Hz to 3.4 kHz
D/A or A/D 8-bit
Active off-hook, and OHT, any Z
T
Figure 2
—
—
Notes:
1.
The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.
2.
Analog signal measured as V
TIP
– V
RING
. Assumes ideal line impedance matching.
3.
The quantization errors inherent in the
μ/A-law
companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4.
V
DD
, V
DDIO
= 3.3 V, V
BAT
= –52 V, no fuse resistors; R
L
= 600
,
Z
S
= 600
synthesized using RS register
coefficients.
5.
The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
6.
0 dBm 0 is equal to 0 dBm into 600
Rev. 1.0
5
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