CAT24AA01, CAT24AA02
1-Kb and 2-Kb I C CMOS Serial EEPROM
FEATURES
Supports Standard and Fast I
2
C Protocol
1.7 V to 5.5 V Supply Voltage Range
16-Byte Page Write Buffer
Hardware Write Protection for entire memory
Schmitt Triggers and Noise Suppression Filters
on I
2
C Bus Inputs (SCL and SDA)
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial temperature range
RoHS-compliant TSOT-23 5-lead and SOIC
8-lead packages
For Ordering Information details, see page 12.
2
DESCRIPTION
The CAT24AA01/24AA02 are 1-Kb and 2-Kb CMOS
Serial EEPROM devices internally organized as
128x8/256x8 bits.
They feature a 16-byte page write buffer and support
both the Standard (100kHz) and the Fast (400kHz)
I
2
C protocols.
In contrast to the CAT24C01/24C02, the
CAT24AA01/24AA02 have no external address
pins, and are therefore suitable in applications
that require a single CAT24AA01/02 on the I
2
C
bus.
PIN CONFIGURATION
SOIC (W)
NC
NC
NC
V
SS
1
2
3
4
8 V
CC
7 WP
6 SCL
5 SDA
TSOT-23 (TD)
SCL
V
SS
SDA
1
2
3
4 V
CC
5 WP
FUNCTIONAL SYMBOL
V
CC
SCL
CAT24AA01
CAT24AA02
WP
SDA
* For the location of Pin 1, please consult the corresponding
package drawing.
V
SS
PIN FUNCTIONS
Pin Name
SDA
SCL
WP
V
CC
V
SS
Function
Serial Data/Address
Clock Input
Write Protect
Power Supply
Ground
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-1120 Rev. B
CAT24AA01, CAT24AA02
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Storage Temperature
Voltage on any Pin with Respect to Ground
(2)
REABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/Erase Cycles
Years
Ratings
–65 to +150
–0.5 to +6.5
Units
ºC
V
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.7 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
I
CCR
I
CCW
I
SB
I
L
V
IL
V
IH
V
OL1
V
OL2
Parameter
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
< 2.5 V, I
OL
= 1.0 mA
Test Conditions
Read, f
SCL
= 400 kHz
Write
All I/O Pins at GND or V
CC
Pin at GND or V
CC
-0.5
V
CC
x 0.7
Min
Max
0.5
1
1
1
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
Units
mA
mA
μA
μA
V
V
V
V
PIN IMPEDANCE CHARACTERISTICS
V
CC
= 1.7 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
C
IN
(3)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
Conditions
V
IN
= 0V
V
IN
= 0V
V
IN
< V
IH
V
IN
> V
IH
Max
8
6
100
1
Units
pF
pF
μA
C
IN(3)
I
WP(5)
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than V
CC
+ 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than V
CC
+ 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode @ 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull-down reverts to a weak current source.
Doc. No. MD-1120 Rev. B
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24AA01, CAT24AA02
A.C. CHARACTERISTICS
V
CC
= 1.7 V to 5.5 V, T
A
= -40°C to 85°C.
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F(2)
t
SU:STO
t
BUF
t
AA
t
DH
T
i(2)
t
SU:WP
t
HD:WP
t
WR
t
PU(2, 3)
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
0
2.5
5
1
100
100
0
2.5
5
1
4
4.7
3.5
100
100
4
4.7
4
4.7
0
250
1000
300
0.6
1.3
0.9
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
Min
Fast
Max
400
Units
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
μs
ns
ns
μs
μs
ms
ms
(1)
A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2 x V
CC
to 0.8 x V
CC
≤
50ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source: I
OL
= 3mA (V
CC
≥
2.5V); I
OL
= 1mA (V
CC
< 2.5V); C
L
= 100pF
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-1120 Rev. B
CAT24AA01, CAT24AA02
POWER-ON RESET (POR)
Each CAT24AA01/02 incorporates Power-On Reset
(POR) circuitry which protects the internal logic
against powering up in the wrong state. The device
will power up into Standby mode after V
CC
exceeds
the POR trigger level and will power down into Reset
mode when V
CC
drops below the POR trigger level.
This bi-directional POR behavior protects the
device against brown-out failure, following a
temporary loss of power.
FUNCTIONAL DESCRIPTION
The CAT24AA01/02 supports the Inter-Integrated
Circuit (I
2
C) Bus protocol. The protocol relies on the
use of a Master device, which provides the clock and
directs bus traffic, and Slave devices which execute
requests. The CAT24AA01/02 operates as a Slave
device. Both Master and Slave can transmit or
receive, but only the Master can assign those roles.
I
2
C BUS PROTOCOL
The 2-wire I
2
C bus consists of two lines, SCL and
SDA, connected to the V
CC
supply via pull-up
resistors. The Master provides the clock to the SCL
line, and the Master and Slaves drive the SDA line. A
‘0’ is transmitted by pulling a line LOW and a ‘1’ by
releasing it HIGH. Data transfer may be initiated only
when the bus is not busy (see A.C. Characteristics).
During data transfer, SDA must remain stable while
SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a
START or STOP condition (Figure 1). A START is
generated by a HIGH to LOW transition, while a
STOP is generated by a LOW to HIGH transition. The
START acts like a wake-up call. Absent a START, no
Slave will respond to the Master. The STOP
completes all commands.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8-bit Slave
address (Figure 2). The first four bits of the Slave
address are 1010 (Ah).
For the CAT24AA01/02 the next three bits must
be 000.
PIN DESCRIPTION
SCL:
The Serial Clock input pin accepts the clock
signal generated by the Master.
SDA:
The Serial Data I/O pin accepts input data and
delivers output data. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and
delivered on the negative edge of SCL.
WP:
When the Write Protect input pin is forced HIGH
by an external source, all write operations are
inhibited. When the pin is not driven by an external
source, it is pulled LOW internally.
¯¯
The last bit, R/W , instructs the Slave to either provide
(1) or accept (0) data, i.e. it signals a Read (1) or a
Write (0) request.
Acknowledge
During the 9
th
clock cycle following every byte sent
onto the bus, the transmitter releases the SDA line,
allowing the receiver to respond. The receiver then
either acknowledges (ACK) by pulling SDA LOW, or
does not acknowledge (NoACK) by letting SDA stay
HIGH (Figure 3). Bus timing is illustrated in Figure 4.
Doc. No. MD-1120 Rev. B
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24AA01, CAT24AA02
Figure 1: Start/Stop Timing
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2: Slave Address Bits
1
0
1
0
0
0
0
¯¯
R/W
Figure 3: Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
ACK SETUP (≥ tSU:DAT)
Figure 4: Bus Timing
tF
tLOW
SCL
tHIGH
tR
tLOW
tSU:STA
SDA IN
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tAA
tDH
tBUF
SDA OUT
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-1120 Rev. B
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