Serial EEPROM Series
High Reliability Series
2
EEPROMs I C BUS
BR24L□□-W Series,BR24S□□□-W Series
No.09001EDT04
ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides
a failsafe method of data reliability, while a double reset function prevents data miswriting. In addition, gold pads and gold
wires are used for internal connections, pushing the boundaries of reliability to the limit.
BR24L□□-W Series assort 1Kbit½64Kbit. BR24S□□□-W Series are possible to operate at high speed in low voltage
and assort 8Kbit½256Kbit.
Contents
BR24L□□-W Series
BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W,
BR24L16-W, BR24L32-W, BR24L64-W
・・・・P2
BR24S□□□-W Series
BR24S08-W, BR24S16-W, BR24S32-W, BR24S64-W,
BR24S128-W, BR24S256-W
・・・P20
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1/40
2009.09 - Rev.D
BR24L□□-W Series,BR24S□□□-W Series
Serial EEPROM Series
Technical Note
High Reliability Series
2
EEPROMs I C BUS
BR24L□□-W Series
●Description
2
BR24L□□-W series is a serial EEPROM of I C BUS interface method.
●Features
2
1) Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock(SCL) and serial data(SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port
*1
3) 1.8V~5.5V single power source action most suitable for battery use
4) Page write mode useful for initial value write at factory shipment
5) Highly reliable connection by Au pad and Au wire
6) Auto erase and auto end function at data rewrite
7) Low current consumption
*2
At write operation (5V)
: 1.2mA (Typ.)
At read operation (5V)
: 0.2mA (Typ.)
At standby operation (5V) : 0.1μA (Typ.)
8) Write mistake prevention function
Write (write protect) function added
9) Write mistake prevention function at low voltage
10) SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J/VSON008X2030 compact package
*3
11) Data rewrite up to 1,000,000 times
12) Data kept for 40 years
13) Noise filter built in SCL / SDA terminal
14) Shipment data all address FFh
*1 BR24L02-W, BR24L16-W, BR24L32-W : 1.7½5.5V
*2 BR24L32-W, BR24L64-W : 1.5mA
*3 Refer to following list
●Page
write
Number of
Pages
Product
number
●BR24L
series
Capacity
1Kbit
2Kbit
4Kbit
8Kbit
16Kbit
32Kbit
64Kbit
Bit
format
128×8
256×8
512×8
1K×8
2K×8
4K×8
8K×8
8Byte
BR24L01A-W
BR24L02-W
16Byte
BR24L04-W
BR24L08-W
BR24L16-W
32Byte
BR24L32-W
BR24L64-W
Type
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
Power source
Voltage
1.8½5.5V
1.7½5.5V
1.8½5.5V
1.8½5.5V
1.7½5.5V
1.7½5.5V
1.8½5.5V
SOP8
●
●
●
●
●
●
●
SOP-J8
●
●
●
●
●
●
●
SSOP-B8 TSSOP-B8
●
●
●
●
●
●
●
●
●
●
●
●
MSOP8
●
●
●
●
●
TSSOP-B8J
●
●
●
●
●
VSON008
X2030
●
●
●
●
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© 2009 ROHM Co., Ltd. All rights reserved.
2/40
2009.09 - Rev.D
BR24L□□-W Series,BR24S□□□-W Series
●Absolute
maximum ratings (Ta=25℃)
Parameter
Impressed voltage
symbol
V
CC
Limits
-0.3½+6.5
*1
450 (SOP8)
450 (SOP-J8)
*2
300 (SSOP-B8)
*3
330 (TSSOP-B8)
*4
310 (MSOP8)
*5
310 (TSSOP-B8J)
*6
300 (VSON008X2030)
*7
-65½+125
-40½+85
-0.3½Vcc+1.0
Unit
V
Technical Note
Permissible dissipation
Pd
mW
Storage temperature range
Action temperature range
Terminal voltage
Tstg
Topr
-
℃
℃
V
When using at Ta=25℃ or higher, 4.5mW(*1,*2),
3.0mW(*3,*7) 3.3mW(*4),3.1mW(*5,*6) to be reduced per 1℃
●Memory
cell characteristics (Ta=25℃, Vcc=1.8½5.5V)
*1
Limits
Parameter
Min.
Typ.
*2
Number of data rewrite times
1,000,000
-
*2
Data hold years
40
-
○Shipment
data all address FFh
*1 BR24L02/16/32-W : 1.7~5.5V
*2 Not 100% TESTED
Max.
-
-
Unit
Times
Years
●Recommended
operating conditions
Parameter
Power source voltage
Input voltage
*1 BR24L02/16/32-W : 1.7~5.5V
Symbol
Vcc
V
IN
Limits
1.8½5.5
*1
0½Vcc
Unit
V
●Electrical
characteristics (Unless otherwise specified, Ta=-40½+85℃, V
CC
=1.8½5.5V)
*1
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
“HIGH” input voltage 1
“LOW” input voltage 1
“HIGH” input voltage 2
“LOW” input voltage 2
“HIGH” input voltage 3
*3
“HIGH” input voltage 3
*4
“LOW” input voltage 3
*2
“LOW” output voltage 1
“LOW” output voltage 2
Input leak current
Output leak current
Current consumption at
action
Standby current
V
IH1
V
IL1
V
IH2
V
IL2
V
IH3
V
IH3
V
IL3
V
OL1
V
OL2
I
LI
I
LO
I
CC1
I
CC2
I
SB
0.7Vcc
-0.3
*2
0.8Vcc
-0.3
*2
0.8Vcc
0.9Vcc
-0.3
-
-
-1
-1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Vcc +1.0
*2
0.3 Vcc
Vcc +1.0
*2
0.2 Vcc
Vcc +1.0
Vcc +1.0
0.1 Vcc
0.4
0.2
1
1
2.0
3.0
*5
*6
Conditions
V
V
V
V
V
V
V
V
V
μA
μA
mA
mA
μA
2.5≦Vcc≦5.5V
2.5≦Vcc≦5.5V
1.8≦Vcc＜2.5V
1.8≦Vcc＜2.5V
1.7≦Vcc＜1.8V
1.7≦Vcc＜1.8V
1.7≦Vcc＜1.8V
I
OL
=3.0mA, 2.5V≦Vcc≦5.5V, (SDA)
I
OL
=0.7mA, 1.7V≦Vcc＜2.5V, (SDA)
V
IN
=0V½Vcc
V
OUT
=0V½Vcc, (SDA)
Vcc=5.5V,fSCL=400kHz, tWR=5ms,
Byte write, Page write
Vcc=5.5V,fSCL=400kHz
Random read, current read,sequential read
Vcc=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
0.5
2.0
◎Radiation
resistance design is not made.
*1 BR24L02/16/32-W : 1.7½5.5V, *2 BR24L16/32-W, *3 BR24L02/16-W, *4 BR24L32-W
*5 BR24L01A/02/04/08/16-W, *6 BR24L32/64-W
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3/40
2009.09 - Rev.D
BR24L□□-W Series,BR24S□□□-W Series
Technical Note
●Action
timing characteristics (Unless otherwise specified, Ta=
-
40½+85℃, V
CC
=1.8½5.5V)
*1
FAST-MODE
STANDARD-MODE
2.5V≦Vcc≦5.5V
1.8V≦Vcc≦5.5V
Parameter
Symbol
Min.
SCL frequency
Data clock “HIGH“ time
Data clock “LOW“ time
SDA, SCL rise time
SDA, SCL fall time
*2
*2
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
ms
μs
ns
μs
μs
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
400
-
-
0.3
0.3
-
-
-
-
0.9
-
-
-
5
0.1
-
-
--
Min.
-
4.0
4.7
-
-
4.0
4.7
0
250
0.2
0.2
4.7
4.7
-
-
0
0.1
1.0
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
100
-
-
1.0
0.3
-
-
-
-
3.5
-
-
-
5
0.1
-
-
-
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:W
P
-
0.6
1.2
-
-
0.6
0.6
0
100
0.1
0.1
0.6
1.2
-
-
0
0.1
1.0
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA, SCL terminal)
WP hold time
WP setup time
WP valid time
*1 BR24L02/16/32-W : 1.7½5.5V
*2 Not 100% tested
●FAST-MODE
and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds.
100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the
maximum action frequency, so 100kHz clock may be used in FAST-MODE. When power source voltage goes down, action
at high speed is not carried out, therefore, at Vcc=2.5V½5.5V , 400kHz, namely, action is made in FASTMODE. (Action is
made also in STANDARD-MODE) Vcc=1.8V~2.5V is only action in 100kHz STANDARD-MODE.
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4/40
2009.09 - Rev.D
BR24L□□-W Series,BR24S□□□-W Series
●Sync
data input / output timing
tR
SCL
tHD:STA
SDA
(入力)
(input)
tBUF
(出力)
(output)
SDA
tPD
tDH
tSU:DAT
tLOW
tHD:DAT
tF
tHIGH
Technical Note
SCL
tSU:STA
SDA
tHD:STA
tSU:STO
START BIT
STOP BIT
○Input
read at the rise edge of SCL
○Data
output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
Fig.1-(b) Start-stop bit timing
SCL
SCL
SDA
DATA(1)
D1
D0
ACK
DATA(n)
ACK
½WR
SDA
D0
Write data
ACK
½W
R
Stop condition
Start condition
WP
Stop condition
ストップコンディション
(n-th
address)
tSU：WP
½HD：WP
Fig.1-(c) Write cycle timing
SCL
DATA(1)
SDA
D1
D0
ACK
tHIGH:WP
WP
DATA(n)
ACK
tWR
Fig.1-(d) WP timing at write execution
○At
write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
○By
setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data
of address under access is not guaranteed, therefore write it once again.
Fig.1-(e) WP timing at write cance
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5/40
2009.09 - Rev.D
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