3.3 VOLT CMOS
ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9
Integrated Device Technology, Inc.
IDT72V01
IDT72V02
IDT72V03
IDT72V04
FEATURES:
• 3.3V family uses 70% less power than the 5 Volt 7201/
02/03/04 family
• 512 x 9 organization (72V01)
• 1024 x 9 organization (72V02)
• 2048 x 9 organization (72V03)
• 4096 X 9 organization (72V04)
• Functionally compatible with 720x family
• 25 ns access time
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Status Flags: Empty, Half-Full, Full
• Auto-retransmit capability
• Available in 32-pin PLCC and 28-pin SOIC Package (to
be determined)
• Industrial temperature range (-40
o
C to +85
o
C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72V01/72V02/72V03/72V04 are dual-port FIFO
memories that operate at a power supply voltage (Vcc)
between 3.0V and 3.6V. Their architecture, functional opera-
tion and pin assignments are identical to those of the IDT7201/
7202/7203/7204. These devices load and empty data on a
first-in/first-out basis. They use Full and Empty flags to
prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write ( ) and Read ( ) pins. The devices
have a maximum data access time as fast as 25 ns.
The devices utilize a 9-bit wide data array to allow for
control and parity bits at the user’s option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. They also feature a Retransmit ( ) capability
that allows for reset of the read pointer to its initial position
when
is pulsed low to allow for retransmission from the
beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.
The IDT72V01/72V02/72V03/72V04 is fabricated using
IDT’s high-speed CMOS technology. It has been designed for
those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications.
W
R
RT
RT
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D
0
–D
8
)
W
WRITE
CONTROL
RAM
ARRAY
512x 9
1024 x 9
2048 x 9
4096 x 9
WRITE
POINTER
READ
POINTER
R
READ
CONTROL
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q
0
–Q
8
)
RS
RESET
LOGIC
FLAG
LOGIC
EF
FF
XO
/
HF
FL
/
RT
XI
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
EXPANSION
LOGIC
2679 drw 01
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-3033/6
5.08
1
IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9
COMMERCIAL TEMPERATURE RANGE
D
3
D
8
W
D
8
D
3
D
2
D
1
D
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
D
4
D
5
D
6
D
7
FL
/
RT
D
2
D
1
D
0
5
6
7
8
9
10
11
12
13
4 3 2 1 32 31 30
29
28
27
J32-1
26
25
24
23
22
21
14 15 16 17 18 19 20
D
6
D
7
NC
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
GND
RS
EF
XO
/
HF
Q
7
Q
6
Q
5
Q
4
XI
FF
Q
0
Q
1
NC
Q
2
D
5
W
INDEX
V
CC
D
4
PIN CONFIGURATIONS
NC
FL
/
RT
RS
EF
XO
/
HF
Q
7
Q
6
GND
NC
R
2679 drw 02a
Q
3
Q
8
R
Q
4
Q
5
2679 drw 02b
SMALL OUTLINE PACKAGE TO BE DETERMINED
PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
V
TERM
Terminal Voltage
with Respect
to GND
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
I
OUT
DC Output
Current
Com’l.
–0.5 to +7.0
Unit
V
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH(1)
V
IL(2)
Rating
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
—
Typ.
3.3
0
—
—
Max.
3.6
0
V
CC
+0.5
0.8
Unit
V
V
V
V
2679 tbl 03
0 to +70
–55 to +125
–55 to +125
50
°C
°C
°C
mA
NOTE:
1. V
IH
= 2.6V for
XI
input (commercial).
2. 1.5V undershoots are allowed for 10ns once per cycle.
NOTE:
2679 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
CAPACITANCE
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Condition
V
IN
= 0V
V
OUT
= 0V
Max.
8
8
Unit
pF
pF
2679 tbl 02
NOTE:
1. This parameter is sampled and not 100% tested.
5.08
2
IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 3.3 V
±
0.3V, T
A
= 0°C to +70°C)
IDT72V01/72V02/
72V03/72V04
Commercial
t
A
= 25 ns
Symbol
I
LI(1)
I
LO(2)
V
OH
V
OL
I
CC1(3,4)
I
CC2(3)
I
CC3
(L)
(3)
IDT72V01/72V02/
72V03/72V04
Commercial
t
A
= 35 ns
Min.
–1
–10
2.4
—
—
—
—
Typ.
—
—
—
—
35
5
—
Max.
1
10
—
0.4
50
8
0.3
Unit
µA
µA
V
V
mA
mA
mA
2679 tbl 05
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage I
OH
= –2mA
Output Logic “0” Voltage I
OL
= 8mA
Active Power Supply Current
Standby Current (
R
=
W
=
RS
=
FL
/
RT
=V
IH
)
Power Down Current (All Input = V
CC
- 0.2V)
Min.
–1
–10
2.4
—
—
—
—
Typ.
—
—
—
—
35
5
—
Max.
1
10
—
0.4
50
8
0.3
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
R
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
3. I
CC
measurements are made with outputs open (only capacitive loading).
4. Tested at f = 20MHz.
5.08
3
IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 3.3V±0.3V, T
A
= 0°C to +70°C)
Commercial
72V01L25/72V02L25
72V03L25/72V04L25
Symbol
f
S
t
RC
t
A
t
RR
t
RPW
t
RLZ
t
WLZ
t
DV
t
RHZ
t
WC
t
WPW
t
WR
t
DS
t
DH
t
RSC
t
RS
t
RSS
t
RSR
t
RTC
t
RT
t
RTS
t
RTR
t
EFL
t
RTF
t
REF
t
RFF
t
RPE
t
WEF
t
WFF
t
WHF
t
RHF
t
WPF
t
XOL
t
XOH
t
XI
t
XIR
t
XIS
Parameter
Shift Frequency
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
(2)
Read Pulse Low to Data Bus at Low Z
(3)
Write Pulse High to Data Bus at Low Z
(3,4)
Data Valid from Read Pulse High
Read Pulse High to Data Bus at High Z
Write Cycle Time
Write Pulse Width
(2)
Write Recovery Time
Data Set-up Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width
(2)
Reset Set-up Time
(3)
Reset Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width
(2)
Retransmit Set-up Time
(3)
Retransmit Recovery Time
Reset to Empty Flag Low
Retransmit Low to Flags Valid
Read Low to Empty Flag Low
Read High to Full Flag High
Read Pulse Width after
EF
High
Write High to Empty Flag High
Write Low to Full Flag Low
Write Low to Half-Full Flag Low
Read High to Half-Full Flag High
Write Pulse Width after
FF
High
Read/Write to
XO
Low
Read/Write to
XO
High
(3)
Commercial
72V01L35/72V02L35
72V03L35/72V04L35
Min.
—
45
—
10
35
5
10
5
—
45
35
10
18
0
45
35
35
10
45
35
35
10
—
—
—
—
—
35
—
—
—
—
35
—
—
35
10
10
Max.
22.2
—
35
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
—
—
—
45
45
45
30
30
—
30
30
45
45
—
35
35
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2679 tbl 06
Min.
—
35
—
10
25
5
5
5
—
35
25
10
15
0
35
25
25
10
35
25
25
10
—
—
—
—
—
25
—
—
—
—
25
—
—
25
10
10
Max.
28.5
—
25
—
—
—
—
—
18
—
—
—
—
—
—
—
—
—
—
—
—
—
35
35
35
25
25
—
25
25
35
35
—
25
25
—
—
—
t
HFH,FFH
Reset to Half-Full and Full Flag High
XI
Pulse Width
XI
Recovery Time
XI
Set-up Time
(2)
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
5.08
4
IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
2679 tbl 08
5.0V
1.1K
TO
OUTPUT
PIN
680Ω
30pF*
2679 drw 03
or equivalent circuit
Figure 1. Output Load
* Includes scope and jig capacitances.
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D
0
– D
8
)
Data inputs for 9-bit wide data.
the Data Outputs (Q
0
– Q
8
) will return to a high impedance
condition until the next Read operation. When all data has
been read from the FIFO, the Empty Flag (
EF
) will go low,
allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high imped-
ance state. Once a valid write operation has been accom-
plished, the Empty Flag (
EF
) will go high after t
WEF
and a valid
Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from
R
so external changes in
R
will not
affect the FIFO when it is empty.
FIRST LOAD/RETRANSMIT (
FL
/
RT
)
This is a dual-purpose input. In the Depth Expansion Mode,
this pin is grounded to indicate that it is the first loaded (see
Operating Modes). In the Single Device Mode, this pin acts as
the restransmit input. The Single Device Mode is initiated by
grounding the Expansion In (
XI
).
The IDT72V01/72V02/72V03/72V04 can be made to re-
transmit data when the Retransmit Enable control (
RT
) input
is pulsed low. A retransmit operation will set the internal read
pointer to the first location and will not affect the write pointer.
Read Enable (
R
) and Write Enable (
W
) must be in the high
state during retransmit. This feature is useful when less than
512/1024/2048/4096 writes are performed between resets.
The retransmit feature is not compatible with the Depth
Expansion Mode and will affect the Half-Full Flag (
HF
), de-
pending on the relative locations of the read and write point-
ers.
EXPANSION IN (
XI
)
This input is a dual-purpose pin. Expansion In (
XI
) is
grounded to indicate an operation in the single device mode.
Expansion In (
XI
) is connected to Expansion Out (
XO
) of the
previous device in the Depth Expansion or Daisy Chain Mode.
Reset is accomplished whenever the Reset (
RS
) input is
taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after
power up before a write operation can take place.
Both the
Read Enable (
R
) and Write Enable (
W
) inputs must be in
the high state during the window shown in Figure 2, (i.e.,
t
RSS
before the rising edge of
RS
) and should not change
until t
RSR
after the rising edge of
RS
. Half-Full Flag (
HF
)
will be reset to high after Reset (
RS
).
WRITE ENABLE (
W
)
A write cycle is initiated on the falling edge of this input if the
Full Flag (
FF
) is not set. Data set-up and hold times must be
adhered to with respect to the rising edge of the Write Enable
(
W
). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
After half of the memory is filled and at the falling edge of
the next write operation, the Half-Full Flag (
HF
) will be set to
low and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (
HF
) is then
reset by the rising edge of the read operation.
To prevent data overflow, the Full Flag (
FF
) will go low,
inhibiting further write operations. Upon the completion of a
valid read operation, the Full Flag (
FF
) will go high after t
RFF
,
allowing a valid write to begin. When the FIFO is full, the
internal write pointer is blocked from
W
, so external changes
in
W
will not affect the FIFO when it is full.
READ ENABLE (
R
)
A read cycle is initiated on the falling edge of the Read
Enable (
R
) provided the Empty Flag (
EF
) is not set. The data
is accessed on a First-In/First-Out basis, independent of any
ongoing write operations. After Read Enable (
R
) goes high,
CONTROLS:
RESET (
RS
)
OUTPUTS:
FULL FLAG (
FF
)
The Full Flag (
FF
) will go low, inhibiting further write op-
eration, when the write pointer is one location less than the
read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (
RS
), the Full-Flag (
FF
) will go
5.08
5
PCB设计
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