HD49338F/HF
CDS/PGA & 12-bit A/D Converter
REJ03F0107-0200
Rev.2.00
May 20, 2005
Description
The HD49338F/HF is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digital signal processing systems together with a 12-bit A/D converter in a single chip.
Functions
Correlated double sampling
PGA
Offset compensation
Serial interface control
12-bit ADC
Operates using only the 3 V voltage
Corresponds to switching mode of power dissipation and operating frequency
Power dissipation: 150 mW (Typ), maximum frequency: 36 MHz
Power dissipation: 100 mW (Typ), maximum frequency: 25 MHz
ADC direct input mode
Y-IN direct input mode
QFP 48-pin package
Features
Suppresses low-frequency noise output from CCD by the S/H type correlated double sampling.
The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and
registers.
High sensitivity is achieved due to the high S/N ratio and a wide coverage provided by a PG amplifier.
Feedback is used to compensate and reduce the DC offsets including the output DC offset due to PGA gain change and
the CCD offset in the CDS (correlated double sampling) amplifier input.
PGA, standby mode, etc., is achieved via a serial interface.
High precision is provided by a 12-bit-resolution A/D converter.
Rev.2.00 May 20, 2005 page 1 of 22
HD49338F/HF
Pin Arrangement
ADCIN
AV
SS
Y IN
AV
DD
BIAS
BLKC
CDSIN
BLKFB
BLKSH
AV
DD
AV
SS
AV
SS
VRM
VRT
VRB
DV
DD
DV
SS
OEB
DV
DD
DV
DD
DV
SS
CS
SDATA
SCK
36 35 34 33 32 31 30 29 28 27 26 25
37
24
23
38
39
22
40
21
41
20
42
19
43
18
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
DV
DD
(NC)
SPSIG
SPBLK
OBP
PBLK
DV
DD
DV
DD
ADCLK
DV
SS
DV
SS
DRDV
DD
Pin Description
Pin No.
1
2 to 11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Symbol
D0
D1 to D10
D11
DRDV
DD
DV
SS
DV
SS
ADCLK
DV
DD
DV
DD
PBLK
OBP
SPBLK
SPSIG
NC
DV
DD
AV
SS
AV
SS
AV
DD
BLKSH
BLKFB
CDSIN
BLKC
Description
Digital output (LSB)
Digital output
Digital output (MSB)
Output buffer power supply (3 V)
Digital ground (0 V)
Digital ground (0 V)
ADC conversion clock input pin
Digital power supply (3 V)
Digital power supply (3 V)
Preblanking input pin
Optical black pulse input pin
Black level sampling clock input pin
Signal level sampling clock input pin
No connection pin
Output power supply (3 V)
Analog ground (0 V)
Analog ground (0 V)
Analog power supply (3 V)
Black level S/H pin
Black level FB pin
CDS input pin
Black level C pin
I/O
O
O
O
—
—
—
I
—
—
I
I
I
I
—
—
—
—
—
—
—
I
—
Analog(A) or
Digital(D)
D
D
D
D
D
D
D
D
D
D
D
D
D
—
D
A
A
A
A
A
A
A
Rev.2.00 May 20, 2005 page 2 of 22
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
(Top view)
HD49338F/HF
Pin Description
(cont.)
Pin No.
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Note:
Symbol
BIAS
AV
DD
Y IN
AV
SS
ADCIN
VRM
VRT
VRB
DV
DD
DV
SS
1
OEB *
DV
DD
DV
DD
DV
SS
CS
SDATA
SCK
Description
Internal bias pin
Connect a 33 kΩ resistor between BIAS and AV
SS
.
Analog power supply (3 V)
Y input pin
Analog ground (0 V)
ADC input pin
Reference voltage pin 1
Connect a 0.1
µF
ceramic capacitor between VRM and AV
SS
.
Reference voltage pin 3
Connect a 0.1
µF
ceramic capacitor between VRT and AV
SS
.
Reference voltage pin 2
Connect a 0.1
µF
ceramic capacitor between VRB and AV
SS
.
Digital power supply (3 V)
Digital ground (0 V)
Digital output enable pin
Digital power supply (3 V)
Digital power supply (3 V)
Digital ground (0 V)
Serial interface control input pin
Serial data input pin
Serial clock input pin
I/O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
I
Analog(A) or
Digital(D)
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
1. With pull-down resistor.
Rev.2.00 May 20, 2005 page 3 of 22
HD49338F/HF
Input/Output Equivalent Circuit
Pin Name
Digital output
D0 to D11
DIN
STBY
Equivalent Circuit
DV
DD
Digital
output
Digital input
ADCLK, OBP,
SPBLK, SPSIG,
CS, SCK, SDATA,
PBLK, OEB
DV
DD
Digital
input
*1
Note: Only OEB is pulled down to about 70 kΩ.
Analog
CDSIN
AV
DD
CDSIN
Internally
connected
to VRT
ADCIN
ADCIN
AV
DD
Internally
connected
to VRM
Y IN
Y IN
AV
DD
+
−
BLKSH, BLKFB
AV
DD
BLKFB
+
−
BLKSH
VRT, VRM, VRB
+
−
VRT
VRM
VRB
AV
DD
+
−
BIAS
BIAS
AV
DD
Rev.2.00 May 20, 2005 page 4 of 22
HD49338F/HF
Block Diagram
DRDV
DD
ADCLK
SPBLK
SPSIG
DV
DD
AV
DD
DV
SS
AV
SS
16 18 19
ADCIN 27
Y IN 26
Timing
generator
31 16 18 19 19
42 OEB
11 D11
PBLK 26
CDSIN 26
BLKSH 28
BLKC 28
CDS
PGA
12 bit
ADC
10 D10
9 D9
8 D8
7 D7
6 D6
5 D5
4 D4
3 D3
2 D2
D1
D0
BLKFB 29
DC offset
compensation
circuit
Serial
interface
Bias
generator
17
44 45 43
35
32 34 33
VRT
VRM
SCK
OBP
SDATA
Rev.2.00 May 20, 2005 page 5 of 22
BIAS
VRB
CS
Output latch circuit