an Intel company
140/155 Mbit/s
CMI Shaper and
Equaliser for
E4/STM-1/OC-3
GD16360
Preliminary
Features
This signal is fed into an equalizer circuit,
which compensates for the frequency de-
pendant attenuation and reshapes the
signal levels into digital, differential
LVPECL levels.
The transmit path receives a distorted
signal usually improperly terminated and
with high reflections. This signal is origi-
nally a differential LVPECL signal from
the system ASIC.
l
General Description
The GD16360 is a dual transceiver for
transmitting and receiving CMI–signals,
according to the ITU-T G.703 standard.
Basically the chip is used as an interface
between the internal system signals and
the outside world.
The internal system signals are CMI
coded, though distorted and attenuated.
The outside world signals should fully
meet ITU-T G.703.
On the receive side the GD16360 re-
ceives an attenuated signal after passing
through a 75
W
coax cable with a 12.7 dB
attenuation at 78 MHz.
Fully dual transmit/receive IC for
E4/STM-1/OC-3 operations.
Meet G.703 for 140 and 155 Mbit/s
CMI interface:
– Return loss
– Receive sensitivity
– Transmit power
Meet G.775 for LOS detection.
3.3 V LVPECL High speed I/O’s.
CMOS configuration signals.
Power consumption: 500 mW
<target>.
Supply voltage: 3.3 V
(5 V for external cabledriver
connection.)
Package: 48 pin TQFP
(7×7×1.4 mm).
Designed for low cost and volume
production.
l
l
l
l
l
l
l
l
Applications
l
STM-1 or E4 CMI electrical line inter-
faces
Data Sheet Rev.: 6
Block Diagram
TXIN1P
TXIN1N
Shaper
TD
TXOM1P
TXOM1N
MCIP1
LOS
BITA
TD
TXO1P
TXO1N
Line
G.703
CIP1
LOS
BITC
LOS
BITB
RXO1P
RXO1N
RXOEN1
LOOP1
LOS1
PECL
Equaliser
RXIN1P
RXIN1N
BIT1P
BIT1N
Logic
LOS
G.775
TXIN2P
TXIN2N
Shaper
TD
TXOM2P
TXOM2N
MCIP2
LOS
BITA
TD
TXO2P
TXO2N
Line
G.703
CIP2
LOS
BITC
LOS
BITB
RXO2P
RXO2N
RXOEN2
LOOP2
LOS2
PECL
Equaliser
RXIN2P
RXIN2N
BIT2P
BIT2N
Logic
LOS
G.775
Data Sheet Rev.: 6
GD16360
Page 2 of 9
Functional Details
Functionally the GD16360 consists of
two identical blocks, each containing:
u
A transmit channel
u
A receive channel
For the remaining three I/O signals
(BITA/B/C), the criteria for signal detec-
tion is set by the presence of transitions.
If there are no transitions for more than
100 bit periods this signal will go high in-
ternally. Otherwise it will stay low.
The determination of the output open col-
lector signal BITxP/N, will be generated
according to the logic table below.
BITA/B/C/G.775
Receive Channel
CMI Digital Output
OK
FAIL
FAIL
OK
Signal ON
Signal ON
NO Signal
NO Signal
CMI Analog Output
OK
FAIL
FAIL
OK
Signal ON
Signal ON
NO Signal
NO Signal
CMI Analog Input
Signal ON
NO Signal
Signal ON
NO Signal
Transmit Channel
CMI Digital Input
Signal ON
NO Signal
Signal ON
NO Signal
Transmit Channel
Each transmit channel comprises:
u
One differential LVPECL signal input
(shaper)
u
Two cable drivers, providing G.703
interface signals.
The cable drivers can be adjusted indi-
vidually, allowing optimum performance,
with minimum power consumption.
The shaper takes the distorted LVPECL
CMI signals and restores them to a near
square waveform internally. This signal is
sent out through the cable drivers. Both
of which are differential open collector
outputs. Both cable drivers are adjust-
able by use of a current control pin (cur-
rent mirroring).
Receive Channel
Each receive channel comprises:
u
A cable equaliser and a LOS (ITU-T
G.775 compliant Loss Of Signal de-
tector)
u
A selector and an LVPECL output
buffer.
The Equaliser takes the differential ana-
logue input signals, which have been
Öf-attenuated
through the coax,
equalises the signal, and send it to a se-
lector. From the selector the signal goes
to the output LVPECL buffer. This buffer
drives the signal outputs from circuit in-
tended for interconnection to the system
ASIC.
The LOS function monitors the input sig-
nal amplitude and generates a signal ac-
cording to ITU-T G.775.
Hence if there is one or more FAIL condi-
tions, then the overall (-external BITxP/N
monitoring signals) will be low (voltage).
The internal signals BITA, BITB, BITC,
G.775 are OR’ed together.
Loopback Mode
The selector can be used to take the sig-
nal from the transmit channel and send it
out through RXOxx to the system ASIC
by setting the LOOPx high.
Build in Test
The build in test is a monitoring circuit,
which looks at the two input signals as
well as both output signals.
For the input signals for the receiver the
detection is determined by the use of the
ITU-T G.775 LOS function.
Data Sheet Rev.: 6
GD16360
Page 3 of 9
Pin List
Mnemonic:
TXIN1P, TXIN1N
TXIN2P, TXIN2N
TXO1P, TXO1N
TXO2P, TXO2N
TXOM1P, TXOM1N
TXOM2P, TXOM2N
CIP1, CIP2
MCIP1, MCIP2
RXIN1P, RXIN1N
RXIN2P, RXIN2N
RXO1P, RXO1N
RXO2P, RXO2N
RXOEN1
RXOEN2
LOS1
LOS2
LOOP1
LOOP2
BIT1P, BIT1N
Pin Number:
13, 14
24, 23
2, 3
35, 34
6, 7
31, 30
1, 36
5, 32
44, 45
42, 41
17, 16
20, 21
8
29
18
19
9
28
10, 11
Pin Type:
LVPECL-IN
LVPECL-IN
ANL-OUT
ANL-OUT
ANL-OUT
ANL-OUT
ANL
ANL
ANL-IN
ANL-IN
LVPECL-OUT
LVPECL-OUT
CMOS-IN
CMOS-IN
CMOS-OUT
CMOS-OUT
CMOS-IN
CMOS-IN
OPEN-
COLLECTOR
OPEN-
COLLECTOR
PWR
PWR
PWR
PWR
Description:
Distorted, LVPECL signal input, 100 - 1000 mV
PP
Distorted, LVPECL signal input, 100 – 1000 mV
PP
ITU-T G.703 interface, open collector output 26.7 mA nominally
ITU-T G.703 interface, open collector output 26.7 mA nominally
ITU-T G.703 interface, open collector output 26.7 mA nominally.
Monitor cable driver.
ITU-T G.703 interface, open collector output 26.7 mA nominally.
Monitor cable driver.
CML open collector current control input. Connect resistor TBD
W
to VDD + 1.7 V.
CML open collector current control input for Monitor cabledrivers.
Connect resistor TBD
W
to VDD + 1.7 V
ITU-T G.703 input.
f
- Attenuated from coax.
ITU-T G.703 input.
f
- Attenuated from coax.
LVPECL output to system ASIC.
LVPECL output to system ASIC.
When LOW, RXO1P is forced LOW.
When LOW, RXO2P is forced LOW.
ITU-T G.775 LOS detected from RXIN1P/N input. When LOS
flagged, output is LOW.
ITU-T G.775 LOS detected from RXIN2P/N input. When LOS
flagged, output is LOW.
Loop-back selector. When HIGH loop-back in transceiver 1 is
enabled.
Loop-back selector. When HIGH loop-back in transceiver 2 is
enabled.
Build in test for transceiver 1. Determines status of GD16360 and
I/O signals determined from logic table above. If one or more fails
the positive output is low (voltage).
Build in test for transceiver 2. Determines status of GD16360 and
I/O signals determined from logic table above. If one or more fails
the positive output is low (voltage).
Positive power supply 3.3 V for transceiver 1.
Positive power supply 3.3 V for transceiver 2.
0 V power, GND.
0 V power, GND.
Connected to VEE.
BIT2P, BIT2N
27, 26
VDD
VDD
VEE
VEE
Heat sink
4, 12, 15, 22,
33
39, 40, 43, 46,
47
25, 37
38, 48
Data Sheet Rev.: 6
GD16360
Page 4 of 9
Package Pinout
RXIN1N
RXIN2N
RXIN1P
RXIN2P
VDD
VDD
VDD
VDD
47
VDD
VEE
VEE
VEE
48
37
38
39
40
41
42
43
44
45
46
CIP1
TXO1P
TXO1N
VDD
MCIP1
TXOM1P
TXOM1N
RXOEN1
LOOP1
BIT1P
BIT1N
VDD
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
CIP2
TXO2P
TXO2N
VDD
MCIP2
TXOM2P
TXOM2N
RXOEN2
LOOP2
BIT2P
BIT2N
VEE
24
23
22
21
20
19
18
17
16
15
14
Figure 1.
Package 48 pin, Top View
13
VDD
TXIN2P
RXO2N
TXIN2N
RXO2P
LOS2
LOS1
RXO1P
RXO1N
VDD
TXIN1N
TXIN1P
Data Sheet Rev.: 6
GD16360
Page 5 of 9
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
