INTEGRATED CIRCUITS
DATA SHEET
SAA4979H
Sample rate converter with
embedded high quality dynamic
noise reduction and expansion port
Product specification
2002 May 28
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality
dynamic noise reduction and expansion port
CONTENTS
1
2
3
4
5
6
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.2.1
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.4
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.6
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.6.7
7.6.8
7.6.9
7.6.10
7.7
7.8
FEATURES
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Digital processing at 1f
H
level
ITU 656 decoder
Double window and picture-in-picture
processing
Black bar detector
Dynamic noise reduction
Noise estimator
Embedded DRAM
3.5-Mbit field memory
Digital processing at 2f
H
level
Sample rate conversion
Expansion port
Panoramic zoom
Digital colour transient improvement
Y horizontal smart peaking
Non-linear phase filter
Post processing
Triple 10-bit digital-to-analog conversion
Microcontroller
Host interface
I
2
C-bus interface
SNERT-bus
I/O ports
Watchdog timer
Reset
System controller
Read enable output
Read enable input
Input enable
Horizontal deflection
Vertical deflection
Auxiliary display signal
Read enable 2
Output input enable 2
Reset read 2
Reset write 2
Line-locked clock generation
Boundary scan test
8
8.1
8.2
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
15.5
16
17
18
19
SAA4979H
CONTROL REGISTER DESCRIPTION
Host interface detail
Special Function Registers (SFRs)
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
TRANSFER FUNCTIONS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
2002 May 28
2
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality
dynamic noise reduction and expansion port
1
FEATURES
SAA4979H
•
Digital YUV input according to ITU 656 standard
•
4 : 2 : 2 field rate upconversion (50 to 100 Hz or
60 to 120 Hz)
•
3.5-Mbit embedded DRAM
•
Sample rate conversion for linear zoom and
compression
•
Panorama mode
•
Dynamic noise reduction
•
Noise estimator
•
Black bar detection
•
Luminance horizontal smart peaking
•
Digital Colour Transient Improvement (DCTI)
•
Triple 10-bit Digital-to-Analog Converter (DAC)
•
Line-locked PLL
•
Expansion port for SAA4992H and SAA4991WP
•
Double window and Picture-In-Picture (PIP) processing
•
Embedded 80C51 microcontroller
•
32-Kbyte internal ROM (mask programmable)
•
512-byte internal RAM
3
QUICK REFERENCE DATA
SYMBOL
V
DDD
V
DDA
V
DDO
; V
DDI
V
DDP
I
DDD
I
DDA
P
tot
T
amb
4
digital supply voltage
analog supply voltage
I/O supply voltage
protection supply voltage
digital supply current
analog supply current
total power dissipation
ambient temperature
PARAMETER
MIN.
3.0
3.15
3.0
3.0
−
−
−
−20
TYP.
3.3
3.30
3.3
5.0
120
40
−
−
MAX.
3.6
3.45
3.6
5.5
160
50
0.9
+70
UNIT
V
V
V
V
mA
mA
W
°C
•
I
2
C-bus controlled
•
Synchronous No parity Eight bit Reception and
Transmission (SNERT) interface
•
Boundary Scan Test (BST).
2
GENERAL DESCRIPTION
The SAA4979H provides an economic stand-alone
solution for 4 : 2 : 2 field rate upconversion (50 to 100 Hz
or 60 to 120 Hz) including the required field memory
combined with picture improvement features and dynamic
field based noise reduction. The IC contains two digital
input channels to allow field or frame based
picture-in-picture processing. It also offers a feature
expansion port for vector based motion estimation and
compensation ICs such as SAA4991WP or SAA4992H.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
QFP128
DESCRIPTION
plastic quad flat package; 128 leads (lead length 1.6 mm);
body 28
×
28
×
3.4 mm; high stand-off height
VERSION
SOT320-2
SAA4979H
2002 May 28
3
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality
dynamic noise reduction and expansion port
5
BLOCK DIAGRAM
SAA4979H
handbook, full pagewidth
LLC1
CLK27
LLC2
SOURCE
SELECT
DI17 to DI10
DI27 to DI20
8
8
MAIN CHANNEL
NOISE
ESTIMATOR
BLACK BAR
DETECTOR
SAA4979H
16
Y [7:0]
H, V
8
16
FAST
SWITCH
2
ITU 656
DECODER 1 16
SUB CHANNEL
16
ITU 656
DECODER 2
H
HREF
PLL
CLK32
DYNAMIC
NOISE
REDUCTION
FIELD
MEMORY
3.5 MBIT
16
EXT_CLK
OSCI
OSCO
CLK32
SAMPLE RATE
CONVERSION
27 to 32 MHz
BYPASS
HD, VD, ADS
REO, IE, OIE2
RE2, RSTR2
REI, RSTW2
ROM
RAM
SOURCE
SELECT
BYPASS
UPSAMPLING
YI7 to YI0
UVI7 to UVI0
SYSTEM CONTROLLER
2
DOWNSAMPLING
H, V
YO7 to YO0
UVO7 to UVO0
RST
P1.2 to P1.5
SNRST
SNDA,SNCL
SDA, SCL
MICROCONTROLLER
I/O
PORT
SNERT-
BUS
I
2
C-BUS
PANORAMIC
ZOOM
LUMINANCE CIRCUIT
10
TRIPLE
10-BIT
DAC
POST
PROCESSING
NON-LINEAR
PHASE
FILTER
HORIZONTAL
SMART
Y PEAKING
Y
BCE
TDI
BLANKING
FRAMING
SIDE PANEL
CHROMINANCE CIRCUIT
10
10
DCTI
UPSAMPLING
4: 2: 2
to
4: 4: 4
UV
BOUNDARY
SCAN
TEST
TCK
TMS
TRST
TDO
YOUT
UOUT
VOUT
MHC186
Fig.1 Block diagram.
2002 May 28
4
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality
dynamic noise reduction and expansion port
6
PINNING
SYMBOL
V
DDO1
RSTR2
RE2
OIE2
V
SSO1
RSTW2
DI10
DI11
DI12
DI13
DI14
DI15
DI16
DI17
V
SSD1
LLC1
V
DDD1
V
DDP
DI20
DI21
DI22
DI23
DI24
DI25
DI26
DI27
V
SSD2
LLC2
V
DDD2
TCK
TDI
TMS
TRST
n.c.
TDO
V
DDA1
YOUT
V
SSA1
UOUT
V
DDA2
2002 May 28
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34 to 41
42
43
44
45
46
47
supply
digital output (test input)
digital output (test input)
digital output (test input)
ground
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
ground
digital input
supply
supply
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
ground
digital input
supply
digital input
digital input
digital input
digital input
−
digital output
supply
analog output
ground
analog output
supply
TYPE
reset read, source 2
read enable, source 2
output/input enable, source 2
I/O ground 1
reset write, source 2
ITU 656 input bit 0 (LSB), source 1
ITU 656 input bit 1, source 1
ITU 656 input bit 2, source 1
ITU 656 input bit 3, source 1
ITU 656 input bit 4, source 1
ITU 656 input bit 5, source 1
ITU 656 input bit 6, source 1
ITU 656 input bit 7 (MSB), source 1
digital ground 1
27 MHz clock signal, source 1
digital supply voltage 1 (3.3 V)
protection supply voltage (5 V)
ITU 656 input bit 0 (LSB), source 2
ITU 656 input bit 1, source 2
ITU 656 input bit 2, source 2
ITU 656 input bit 3, source 2
ITU 656 input bit 4, source 2
ITU 656 input bit 5, source 2
ITU 656 input bit 6, source 2
ITU 656 input bit 7 (MSB), source 2
digital ground 2
27 MHz clock signal, source 2
digital supply voltage 2 (3.3 V)
test clock
test data input
test mode select
test reset (active LOW)
not connected
test data output
analog supply voltage 1 (3.3 V)
Y analog output
analog ground 1
−(B −
Y) analog output
analog supply voltage 2 (3.3 V)
5
DESCRIPTION
I/O supply voltage 1 (3.3 V)
SAA4979H
FPGA/CPLD
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