Hitachi Single-Chip Microcomputer
H8/3437 Series
H8/3437
HD6473437, HD6433437
H8/3436
HD6433436
H8/3434
HD6473434, HD6433434
H8/3434 F-ZTAT
TM
HD64F3434
H8/3437 F-ZTAT
TM
HD64F3437
Hardware Manual
ADE-602-077C
Preface
The H8/3437 Series is a series of high-performance microcontrollers with a fast H8/300 CPU core
and a set of on-chip supporting functions optimized for embedded control. These include ROM,
RAM, four types of timers, a serial communication interface, optional I
2
C bus interface, host
interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system
configurations, so that compact, high-performance systems can be implemented easily. The series
includes the H8/3437 with 60-kbyte ROM and 2-kbyte RAM, the H8/3436 with 48-kbyte ROM and
2-kbyte RAM, and the H8/3434 with 32-kbyte ROM and 1-kbyte RAM.
The H8/3437, H8/3436, and H8/3434 are available in mask-ROM versions. The H8/3437 and
H8/3434 are also available in ZTAT™
*1
(zero turn-around time) versions, providing a quick and
flexible response to conditions from ramp-up through full-scale volume production, even for
applications with frequently-changing specifications. In addition, the H8/3434 and H8/3437 have
F-ZTAT™
*2
(flexible-ZTAT) versions with on-board programmability.
This manual describes the hardware of the H8/3437 Series. Refer to the
H8/300 Series
Programming Manual
for a detailed description of the instruction set.
Notes: 1. ZTAT™ is a trademark of Hitachi, Ltd.
2. F-ZTAT™ is a trademark of Hitachi, Ltd.
Main Amendments and Additions in this Edition
Page
All
Title
Addition of H8/3437F-ZTAT version
Addition of ROM descriptions
Section 18 Mask ROM Version/ZTAT Version
Section 19 32-Kbyte Flash Memory Version
Section 20 60-Kbyte Flash Memory Version
491
495
498
505
Table 22-2
Table 22-3
Table 22-4
DC Characteristics (5-V Version)
DC Characteristics (4-V Version)
DC Characteristics (3-V Version)
Values changed for “Input capacitance”
item
Values changed for “Input capacitance”
item
Values changed for “Input capacitance”
item
Values changed for “HIF write cycle”
item
Amendment/Addition
Table 22-10 Timing Conditions of On-Chip
Supporting Modules
Contents
Section 1
1.1
1.2
1.3
Overview
.....................................................................................................
Overview ........................................................................................................................
Block Diagram................................................................................................................
Pin Assignments and Functions......................................................................................
1.3.1
Pin Arrangement.............................................................................................
1.3.2
Pin Functions ..................................................................................................
1
1
5
6
6
7
Section 2
2.1
CPU
............................................................................................................... 17
17
17
18
18
19
19
19
20
21
22
23
24
24
26
30
31
33
34
34
36
41
43
44
46
46
47
47
47
48
48
50
2.2
2.3
2.4
2.5
2.6
2.7
Overview ........................................................................................................................
2.1.1
Features...........................................................................................................
2.1.2
Address Space.................................................................................................
2.1.3
Register Configuration....................................................................................
Register Descriptions......................................................................................................
2.2.1
General Registers............................................................................................
2.2.2
Control Registers ............................................................................................
2.2.3
Initial Register Values ....................................................................................
Data Formats...................................................................................................................
2.3.1
Data Formats in General Registers .................................................................
2.3.2
Memory Data Formats....................................................................................
Addressing Modes ..........................................................................................................
2.4.1
Addressing Mode............................................................................................
2.4.2
Calculation of Effective Address....................................................................
Instruction Set.................................................................................................................
2.5.1
Data Transfer Instructions ..............................................................................
2.5.2
Arithmetic Operations ....................................................................................
2.5.3
Logic Operations ............................................................................................
2.5.4
Shift Operations ..............................................................................................
2.5.5
Bit Manipulations ...........................................................................................
2.5.6
Branching Instructions....................................................................................
2.5.7
System Control Instructions ...........................................................................
2.5.8
Block Data Transfer Instruction .....................................................................
CPU States ......................................................................................................................
2.6.1
Overview.........................................................................................................
2.6.2
Program Execution State ................................................................................
2.6.3
Exception-Handling State...............................................................................
2.6.4
Power-Down State ..........................................................................................
Access Timing and Bus Cycle........................................................................................
2.7.1
Access to On-Chip Memory (RAM and ROM) .............................................
2.7.2
Access to On-Chip Register Field and External Devices ...............................
Section 3
3.1
MCU Operating Modes and Address Space
..................................... 53
53
53
54
54
57
58
3.2
3.3
3.4
Overview ........................................................................................................................
3.1.1
Mode Selection ...............................................................................................
3.1.2
Mode and System Control Registers .............................................................
System Control Register (SYSCR).................................................................................
Mode Control Register (MDCR) ....................................................................................
Address Space Map in Each Operating Mode................................................................
Section 4
4.1
4.2
Exception Handling
.................................................................................. 61
61
61
61
61
64
64
64
66
70
70
71
76
77
78
4.3
4.4
Overview ........................................................................................................................
Reset
........................................................................................................................
4.2.1
Overview.........................................................................................................
4.2.2
Reset Sequence ...............................................................................................
4.2.3
Disabling of Interrupts after Reset..................................................................
Interrupts ........................................................................................................................
4.3.1
Overview.........................................................................................................
4.3.2
Interrupt-Related Registers.............................................................................
4.3.3
External Interrupts ..........................................................................................
4.3.4
Internal Interrupts ...........................................................................................
4.3.5
Interrupt Handling ..........................................................................................
4.3.6
Interrupt Response Time.................................................................................
4.3.7
Precaution .......................................................................................................
Note on Stack Handling..................................................................................................
Section 5
5.1
Wait-State Controller
............................................................................... 79
79
79
79
80
80
80
80
82
5.2
5.3
Overview ........................................................................................................................
5.1.1
Features...........................................................................................................
5.1.2
Block Diagram................................................................................................
5.1.3
Input/Output Pins............................................................................................
5.1.4
Register Configuration....................................................................................
Register Description .......................................................................................................
5.2.1
Wait-State Control Register (WSCR).............................................................
Wait Modes.....................................................................................................................
Section 6
6.1
Clock Pulse Generator
............................................................................. 85
85
85
86
87
92
92
6.2
6.3
6.4
Overview ........................................................................................................................
6.1.1
Block Diagram................................................................................................
6.1.2
Wait-State Control Register (WSCR).............................................................
Oscillator Circuit ............................................................................................................
Duty Adjustment Circuit.................................................................................................
Prescaler ........................................................................................................................
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
